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Omid Shoaei :
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Ali Zahabi , Omid Shoaei , Yarallah Koolivand , Parviz Jabedar-Maralani A two-stage genetic algorithm method for optimization the Sigma-Delta modulators. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2005, pp:1212-1215 [Conf ] Vahid Majidzadeh , Omid Shoaei Arbitrary design of high order noise transfer function for a novel class of reduced-sample-rate sigma-delta-pipeline ADCs. [Citation Graph (0, 0)][DBLP ] DATE, 2006, pp:138-143 [Conf ] Mohammad Taherzadeh-Sani , Reza Lotfi , Omid Shoaei Systematic Design for Optimization of High-Resolution Pipelined ADCs. [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:678-679 [Conf ] Mohammad Yavari , Omid Shoaei , Ángel Rodríguez-Vázquez Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation. [Citation Graph (0, 0)][DBLP ] DATE, 2006, pp:144-149 [Conf ] Mohammad Yavari , Omid Shoaei , Ángel Rodríguez-Vázquez Double-sampling single-loop sigma-delta modulator topologies for broadband applications. [Citation Graph (0, 0)][DBLP ] DATE, 2006, pp:399-404 [Conf ] Yarallah Koolivand , Omid Shoaei , A. Fotowat-Ahmadi , Ali Zahabi , Parviz Jabedar-Maralani Nonlinearity Analysis in ISD CMOS LNA's Using Volterra Series. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2006, pp:135-139 [Conf ] Vahid Majidzadeh , Omid Shoaei A power optimized design methodology for low-distortion sigma-delta-pipeline ADCs. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2006, pp:284-289 [Conf ] Reza Lotfi , Mohammad Taherzadeh-Sani , M. Yaser Azizi , Omid Shoaei Systematic Design for Power Minimization of Pipelined Analog-to-Digital Converters. [Citation Graph (0, 0)][DBLP ] ICCAD, 2003, pp:371-374 [Conf ] Mohammad Taherzadeh-Sani , Reza Lotfi , Omid Shoaei A Statistical Approach to Estimate the Dynamic Non-Linearity Parameters of Pipeline ADCs. [Citation Graph (0, 0)][DBLP ] ICCAD, 2003, pp:367-370 [Conf ] Nima Maghari , Omid Shoaei A dynamic start-up circuit for low voltage CMOS current mirrors with power-down support. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2005, pp:4265-4268 [Conf ] Nima Maghari , Mohammad Yavari , Omid Shoaei An analytical model for the slewing behavior of CMOS two-stage operational transconductance amplifiers. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 2004, pp:553-556 [Conf ] Reza Lotfi , Mohammad Taherzadeh-Sani , Omid Shoaei A 12-bit 40MSPS 3.3-V 56-mW pipelined A/D convereter in 0.25-µm CMOS [convereter read converter]. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 2004, pp:69-72 [Conf ] Reza Lotfi , Mohammad Taherzadeh-Sani , Omid Shoaei Power consumption issues in high-speed high-resolution pipelined A/D converters. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2005, pp:4618-4621 [Conf ] Babak Nejati , Omid Shoaei A 10-bit, 3.3-V, 60MSample/s, combined radix<2 and 1.5-bit/stage pipelined analog-to-digital converter. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 2004, pp:73-76 [Conf ] Omid Shoaei , W. Martin Snelgrove Optimal (Bandpass) Continuous-Time Sigma-Delta Modulator. [Citation Graph (0, 0)][DBLP ] ISCAS, 1994, pp:489-492 [Conf ] Omid Shoaei , W. Martin Snelgrove A Multi-Feedback Design for LC Bandpass Delta-Sigma Modulators. [Citation Graph (0, 0)][DBLP ] ISCAS, 1995, pp:171-174 [Conf ] Mohammad Taherzadeh-Sani , Reza Lotfi , Omid Shoaei A pseudo-class-AB telescopic-cascode operational amplifier. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 2004, pp:737-740 [Conf ] Mohammad Yavari , Omid Shoaei Low-voltage sigma-delta modulator topologies for broadband applications. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 2004, pp:465-468 [Conf ] Mohammad Yavari , Omid Shoaei High-order single-loop double-sampling sigma-delta modulator topologies for broadband applications. [Citation Graph (0, 0)][DBLP ] ISCAS (6), 2005, pp:5593-5596 [Conf ] Mohammad Yavari , Omid Shoaei , Ali Afzali-Kusha A very low-voltage, low-power and high resolution sigma-delta modulator for digital audio in 0.25µm CMOS. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 2003, pp:1045-1048 [Conf ] Mohammad Yavari , Omid Shoaei , Francesco Svelto Hybrid cascode compensation for two-stage CMOS operational amplifiers. [Citation Graph (0, 0)][DBLP ] ISCAS (2), 2005, pp:1565-1568 [Conf ] Hashem Zare-Hoseini , Omid Shoaei , Izzet Kale A new multiply-by-two gain-stage with enhanced immunity to capacitor-mismatch. [Citation Graph (0, 0)][DBLP ] ISCAS (2), 2005, pp:1409-1412 [Conf ] Babak Nejati , Omid Shoaei A 10-bit, 2.5-V, 40 M sample/s, pipelined analog-to-digital converter in 0.6-um CMOS. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 2001, pp:576-579 [Conf ] P. Amini , Omid Shoaei A low-power gigabit Ethernet analog equalizer. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 2001, pp:176-179 [Conf ] H. Zarei , Omid Shoaei , Seid Mehdi Fakhraie A low-power fully integrated Gaussian-MSK modulator based on the sigma-delta fractional-N frequency synthesis. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 2001, pp:100-103 [Conf ] J. Talebzadeh , M. R. Hasanzadeh , Mohammad Yavari , Omid Shoaei A 10-bit 150-MS/s, parallel pipeline A/D converter in 0.6-µm CMOS. [Citation Graph (0, 0)][DBLP ] ISCAS (3), 2002, pp:133-136 [Conf ] Reza Lotfi , Mohammad Taherzadeh-Sani , M. Yaser Azizi , Omid Shoaei A low-power design methodology for high-resolution pipelined analog-to-digital converters. [Citation Graph (0, 0)][DBLP ] ISLPED, 2003, pp:334-339 [Conf ] Mohammad Yavari , Omid Shoaei Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switched-capacitor applications. [Citation Graph (0, 0)][DBLP ] ISLPED, 2003, pp:345-348 [Conf ] Ali Zahabi , Omid Shoaei , Yarallah Koolivand Design of a Band-Pass Pseudo-2-Path Switched Capacitor Ladder Filter. [Citation Graph (0, 0)][DBLP ] ISQED, 2005, pp:662-667 [Conf ] Yarallah Koolivand , Omid Shoaei , Ali Zahabi , Parviz Jabedar-Maralani A complete analysis of noise in inductively source degenerated CMOS LNA's. [Citation Graph (0, 0)][DBLP ] IEICE Electronic Express, 2005, v:2, n:1, pp:25-31 [Journal ] Hossein Shamsi , Omid Shoaei Return to-zero feedback insertion in a continuous time Delta-Sigma modulator for excess loop delay compensation. [Citation Graph (0, 0)][DBLP ] IEICE Electronic Express, 2004, v:1, n:18, pp:568-574 [Journal ] Mohammad Yavari , Omid Shoaei A novel fully-differential class AB folded-cascode OTA. [Citation Graph (0, 0)][DBLP ] IEICE Electronic Express, 2004, v:1, n:13, pp:358-362 [Journal ] Ali Zahabi , Omid Shoaei , Yarallah Koolivand , Parviz Jabedar-Maralani A 2/5mW CMOS Delta Sigma modulator employed in an improved GSM/UMTS receiver structure. [Citation Graph (0, 0)][DBLP ] IEICE Electronic Express, 2005, v:2, n:8, pp:267-273 [Journal ] Reza Lotfi , Mohammad Taherzadeh-Sani , M. Yaser Azizi , Omid Shoaei Low-power design techniques for low-voltage fast-settling operational amplifiers in switched-capacitor applications. [Citation Graph (0, 0)][DBLP ] Integration, 2003, v:36, n:4, pp:175-189 [Journal ] Babak Nejati , Omid Shoaei Systematic design of the pipelined analog-to-digital converter with radix<2. [Citation Graph (0, 0)][DBLP ] Microelectronics Journal, 2004, v:35, n:9, pp:767-776 [Journal ] Mohammad Yavari , Omid Shoaei , Ángel Rodríguez-Vázquez Double-sampled cascaded sigma-delta modulator topologies for low oversampling ratios. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] M. B. Vahidfar , Omid Shoaei , M. Fardis A low power, transverse analog FIR filter for feed forward equalization of gigabit Ethernet. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] B. Tavassoli , Omid Shoaei Digital background calibration of pipeline ADC with open-loop gain stage. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Hossein Shamsi , Omid Shoaei A novel structure for the design of 2-1-1 cascaded continuous time delta sigma modulators. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Hashem Zare-Hoseini , Omid Shoaei , Izzet Kale A new structure for capacitor-mismatch-insensitive multiply-by-two amplification. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] S. M. Mortazavi Zanjani , S. Rahimian Omam , Seid Mehdi Fakhraie , Omid Shoaei Experimental Evaluation of Different Realizations of Recursive CIC Filters. [Citation Graph (0, 0)][DBLP ] CCECE, 2006, pp:1056-1059 [Conf ] New technique in design of active rf cmos mixers for low flicker noise and high conversion gain. [Citation Graph (, )][DBLP ] A low-power /spl Delta//spl Sigma/ modulator with low capacitor spread for multi-standard receiver applications. [Citation Graph (, )][DBLP ] A CMOS high IIP2 mixer for multi-standard receivers. [Citation Graph (, )][DBLP ] A new technique for design CMOS LNA for multi-standard receivers. [Citation Graph (, )][DBLP ] An IIP2 calibration technique for CMOS multi-standard mixers. [Citation Graph (, )][DBLP ] A 0.9V 10-bit 100 MS/s switched-RC pipelined ADC without using a front-end S/H in 90nm CMOS. [Citation Graph (, )][DBLP ] A New Approach for DAC Non-linearity Compensation in Continuous Time Delta Sigma Modulators. [Citation Graph (, )][DBLP ] Continuous Time Delta-Sigma Modulators with Arbitrary DAC Waveforms. [Citation Graph (, )][DBLP ] A six-order wideband bandpass sigma-delta modulator. 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