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Yarallah Koolivand :
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Ali Zahabi , Omid Shoaei , Yarallah Koolivand , Parviz Jabedar-Maralani A two-stage genetic algorithm method for optimization the Sigma-Delta modulators. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2005, pp:1212-1215 [Conf ] Yarallah Koolivand , Omid Shoaei , A. Fotowat-Ahmadi , Ali Zahabi , Parviz Jabedar-Maralani Nonlinearity Analysis in ISD CMOS LNA's Using Volterra Series. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2006, pp:135-139 [Conf ] Yarallah Koolivand , Ali Zahabi , Nasser Masoumi Modeling of polysilicide gate resistance effect on inverter delay and power consumption using distributed RC method and branching technique. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2004, pp:149-153 [Conf ] Ali Zahabi , Omid Shoaei , Yarallah Koolivand Design of a Band-Pass Pseudo-2-Path Switched Capacitor Ladder Filter. [Citation Graph (0, 0)][DBLP ] ISQED, 2005, pp:662-667 [Conf ] Yarallah Koolivand , Omid Shoaei , Ali Zahabi , Parviz Jabedar-Maralani A complete analysis of noise in inductively source degenerated CMOS LNA's. [Citation Graph (0, 0)][DBLP ] IEICE Electronic Express, 2005, v:2, n:1, pp:25-31 [Journal ] Ali Zahabi , Omid Shoaei , Yarallah Koolivand , Parviz Jabedar-Maralani A 2/5mW CMOS Delta Sigma modulator employed in an improved GSM/UMTS receiver structure. [Citation Graph (0, 0)][DBLP ] IEICE Electronic Express, 2005, v:2, n:8, pp:267-273 [Journal ] New technique in design of active rf cmos mixers for low flicker noise and high conversion gain. [Citation Graph (, )][DBLP ] A low-power /spl Delta//spl Sigma/ modulator with low capacitor spread for multi-standard receiver applications. [Citation Graph (, )][DBLP ] A new technique for design CMOS LNA for multi-standard receivers. [Citation Graph (, )][DBLP ] Search in 0.001secs, Finished in 0.002secs