The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

X. Zeng: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. X. Zeng, P. S. Tang, C. K. Tse
    Design of Nonlinear Switched-Current Circuits Using Building Block Approach. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:409-414 [Conf]
  2. X. Zeng, P. Bowron, A. A. Muhieddine
    HD and IMD Prediction Techniques for Active Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:169-172 [Conf]
  3. W. Li, D. Zhou, H. Kim, X. Zeng
    Automatic clock tree design with IPs in the system. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:387-390 [Conf]
  4. X. Zeng, D. Zhou
    Design of GHz VLSI clock distribution circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:391-394 [Conf]
  5. X. Zeng, J. Guan, W. Q. Zhao, P. S. Tang, D. Zhou
    A constraint-based placement refinement method for CMOS analog cell layout. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:408-411 [Conf]
  6. X. Zeng, D. Zhou, Wei Li
    Buffer insertion for clock delay and skew minimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:36-41 [Conf]
  7. F. Tian, Y. Huang, X. Zeng, L. Hong
    Gene, Wavelet, Fractal and Data Compression. [Citation Graph (0, 0)][DBLP]
    WAA, 2003, pp:27-33 [Conf]
  8. X. Zeng, X. Tan
    PN Code Acquistion Dection for CDMA Networks Based on Wavelet Transform and Artifical Neural Network. [Citation Graph (0, 0)][DBLP]
    WAA, 2003, pp:495-502 [Conf]

Search in 0.003secs, Finished in 0.004secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002