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Alan Mishchenko: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch
    Detecting support-reducing bound sets using two-cofactor symmetries. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:266-271 [Conf]
  2. Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
    DAG-aware AIG rewriting a fresh look at combinational logic synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:532-535 [Conf]
  3. Alan Mishchenko, Tsutomu Sasao
    Large-scale SOP minimization using decomposition and functional properties. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:149-154 [Conf]
  4. Alan Mishchenko, Bernd Steinbach, Marek A. Perkowski
    An Algorithm for Bi-Decomposition of Logic Functions. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:103-108 [Conf]
  5. Alan Mishchenko, Xinning Wang, Timothy Kam
    A new enhanced constructive decomposition and mapping algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:143-148 [Conf]
  6. Marek A. Perkowski, Rahul Malvi, Stan Grygiel, Michael Burns, Alan Mishchenko
    Graph Coloring Algorithms for Fast Evaluation of Curtis Decompositions. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:225-230 [Conf]
  7. Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
    Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:510-515 [Conf]
  8. Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton
    Reducing Multi-Valued Algebraic Operations to Binary. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10752-10757 [Conf]
  9. Alan Mishchenko, Robert K. Brayton
    SAT-Based Complete Don't-Care Computation for Network Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:412-417 [Conf]
  10. Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko
    Efficient Solution of Language Equations Using Partitioned Representations. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:418-423 [Conf]
  11. Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Xiaoyu Song, Anas Al-Rabadi, Bart Massey, Pawel Kerntopf, Andrzej Buller, Lech Józwiak, Alan J. Coppola
    Regular Realization of Symmetric Functions Using Reversible Logic. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:245-253 [Conf]
  12. Marek A. Perkowski, Alan Mishchenko, Anatoli N. Chebotarev
    Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 1999, pp:129-138 [Conf]
  13. Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
    Improvements to technology mapping for LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:41-49 [Conf]
  14. Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Alan J. Coppola, Andrew A. Kennings
    Board-level multiterminal net assignment. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:130-135 [Conf]
  15. Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam
    Reducing structural bias in technology mapping. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:519-526 [Conf]
  16. Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton
    On breakable cyclic definitions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:411-418 [Conf]
  17. Alan Mishchenko, Robert K. Brayton
    Simplification of non-deterministic multi-valued networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:557-562 [Conf]
  18. Alan Mishchenko, Robert K. Brayton
    A Theory of Non-Deterministic Networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:709-717 [Conf]
  19. Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton
    Topologically constrained logic synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:679-686 [Conf]
  20. Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton, Niklas Eén
    Improvements to combinational equivalence checking. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:836-843 [Conf]
  21. Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton
    Factor cuts. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:143-150 [Conf]
  22. Malgorzata Chrzanowska-Jeske, Alan Mishchenko
    Synthesis for regularity using decision diagrams [logic IC synthesis and layout]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4721-4724 [Conf]
  23. Robert K. Brayton, M. Gao, Jie-Hong Roland Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Subarnarekha Sinha, Tiziano Villa
    Optimization of Multi-Valued Multi-Level Networks. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:168-0 [Conf]
  24. Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton
    Reducing Multi-Valued Algebraic Operations to Binary. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:339-344 [Conf]
  25. Alan Mishchenko, Robert K. Brayton
    A Boolean Paradigm in Multi-Valued Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:173-177 [Conf]
  26. Alan Mishchenko, Robert K. Brayton
    Simplification of Non-Deterministic Multi-Valued Networks. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:333-338 [Conf]
  27. Alan Mishchenko, Marek A. Perkowski
    Logic Synthesis of Reversible Wave Cascades. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:197-202 [Conf]
  28. Alan Mishchenko, Tsutomu Sasao
    Encoding of Boolean Functions and its Application to LUT Cascade Synthesis. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:115-120 [Conf]
  29. Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton
    Topologically Constrained Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:13-20 [Conf]
  30. Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
    Using simulation and satisfiability to compute flexibilities in Boolean networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:743-755 [Journal]
  31. Alan Mishchenko
    Fast computation of symmetries in Boolean functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1588-1593 [Journal]
  32. Alan Mishchenko, Robert K. Brayton
    A theory of nondeterministic networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:977-999 [Journal]
  33. Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch
    Linear cofactor relationships in Boolean functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1011-1023 [Journal]
  34. Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Andreas Kuehlmann
    On Resolution Proofs for Combinational Equivalence. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:600-605 [Conf]
  35. Niklas Eén, Alan Mishchenko, Niklas Sörensson
    Applying Logic Synthesis for Speeding Up SAT. [Citation Graph (0, 0)][DBLP]
    SAT, 2007, pp:272-286 [Conf]
  36. Alan Mishchenko, Robert K. Brayton
    SAT-Based Complete Don't-Care Computation for Network Optimization [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  37. Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko
    Efficient Solution of Language Equations Using Partitioned Representations [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  38. Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Andrew A. Kennings, Alan J. Coppola
    Board-level multiterminal net assignment for the partial cross-bar architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:511-514 [Journal]

  39. ABC: An Academic Industrial-Strength Verification Tool. [Citation Graph (, )][DBLP]


  40. Scalable min-register retiming under timing and initializability constraints. [Citation Graph (, )][DBLP]


  41. Merging nodes under sequential observability. [Citation Graph (, )][DBLP]


  42. Speculative reduction-based scalable redundancy identification. [Citation Graph (, )][DBLP]


  43. Sequential logic synthesis using symbolic bi-decomposition. [Citation Graph (, )][DBLP]


  44. Monolithically stackable hybrid FPGA. [Citation Graph (, )][DBLP]


  45. Automated Extraction of Inductive Invariants to Aid Model Checking. [Citation Graph (, )][DBLP]


  46. Recording Synthesis History for Sequential Verification. [Citation Graph (, )][DBLP]


  47. Invariant-Strengthened Elimination of Dependent State Elements. [Citation Graph (, )][DBLP]


  48. Fast Minimum-Register Retiming via Binary Maximum-Flow. [Citation Graph (, )][DBLP]


  49. WireMap: FPGA technology mapping for improved routability. [Citation Graph (, )][DBLP]


  50. Global delay optimization using structural choices. [Citation Graph (, )][DBLP]


  51. Scalable don't-care-based logic optimization and resynthesis. [Citation Graph (, )][DBLP]


  52. SmartOpt: an industrial strength framework for logic synthesis. [Citation Graph (, )][DBLP]


  53. Scalable exploration of functional dependency by interpolation and incremental SAT solving. [Citation Graph (, )][DBLP]


  54. Combinational and sequential mapping with priority cuts. [Citation Graph (, )][DBLP]


  55. Boolean factoring and decomposition of logic networks. [Citation Graph (, )][DBLP]


  56. Scalable and scalably-verifiable sequential synthesis. [Citation Graph (, )][DBLP]


  57. A Single-Instance Incremental SAT Formulation of Proof- and Counterexample-Based Abstraction [Citation Graph (, )][DBLP]


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