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Jiarong Tong: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Feng Zhou, Zhijun Huang, Jiarong Tong, Pushan Tang
    An Analytical Delay Model for SRAM-Based FPGA Interconnections. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:101-104 [Conf]
  2. Rongzheng Zhou, Jiarong Tong, Pushan Tang
    FPART: A Multi-way FPGA Partitioning Procedure Based on the Improved FM Algorithm. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:513-518 [Conf]
  3. Binlin Guo, Jiarong Tong
    A SC-based novel configurable analog cell. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:243- [Conf]
  4. Yirong OuYang, Jiarong Tong
    A New Universal Test Pattern Auto-generating Approach for FPGA Logic Resources (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:263- [Conf]
  5. Wen Yujie, Jiarong Tong, Charles Chiang
    Domain Specific Non-Uniform Routing Architecture for Embedded Programmable IP Core (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:269- [Conf]
  6. Lihong Feng, Xuan Zeng, Jiarong Tong, Charles Chiang, Dian Zhou
    Two-sided projection method in variational equation model order reduction of nonlinear circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:816-819 [Conf]
  7. Jian Wang, Xuan Zeng, Wei Cai, Charles Chiang, Jiarong Tong, Dian Zhou
    Frequency domain wavelet method with GMRES for large-scale linear circuit simulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:321-324 [Conf]

  8. WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design. [Citation Graph (, )][DBLP]


  9. Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays. [Citation Graph (, )][DBLP]


  10. Building a faster boolean matcher using bloom filter. [Citation Graph (, )][DBLP]


  11. Variational capacitance modeling using orthogonal polynomial method. [Citation Graph (, )][DBLP]


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