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Narendra V. Shenoy: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hai Zhou, Narendra V. Shenoy, William Nicholls
    Efficient minimum spanning tree construction without Delaunay triangulation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:192-197 [Conf]
  2. Chi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei
    Emerging markets: design goes global. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:195- [Conf]
  3. Masamichi Kawarabayashi, Narendra V. Shenoy, Alberto L. Sangiovanni-Vincentelli
    A Verification Technique for Gated Clock. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:123-127 [Conf]
  4. Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Logic Synthesis for Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:620-625 [Conf]
  5. Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Resynthesis of Multi-Phase Pipelines. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:490-496 [Conf]
  6. Narendra V. Shenoy, Jamil Kawa, Raul Camposano
    Design automation for mask programmable fabrics. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:192-197 [Conf]
  7. Narendra V. Shenoy, William Nicholls
    An efficient routing database. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:590-595 [Conf]
  8. Narendra V. Shenoy, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    On the Temporal Equivalence of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:405-409 [Conf]
  9. Hai Zhou, Narendra V. Shenoy, William Nicholls
    Timing Analysis with Crosstalk as Fixpoints on Complete Lattice. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:714-719 [Conf]
  10. Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou
    Track assignment: a desirable intermediate step between global routing and detailed routing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:59-66 [Conf]
  11. Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Improved Logic Synthesis Algorithms for Table Look Up Architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:564-567 [Conf]
  12. Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:572-575 [Conf]
  13. Ralph H. J. M. Otten, Lukas P. P. P. van Ginneken, Narendra V. Shenoy
    Embedded tutorial: Speed - new paradigms in design for performance. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:700- [Conf]
  14. Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Graph algorithms for clock schedule optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:132-136 [Conf]
  15. Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Minimum padding to satisfy short path constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:156-161 [Conf]
  16. Narendra V. Shenoy, Richard L. Rudell
    Efficient implementation of retiming. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:226-233 [Conf]
  17. Debjit Sinha, Narendra V. Shenoy, Hai Zhou
    Statistical gate sizing for timing yield optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:1037-1041 [Conf]
  18. Thomas G. Szymanski, Narendra V. Shenoy
    Verifying clock schedules. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:124-131 [Conf]
  19. Ramsey W. Haddad, Lukas P. P. P. van Ginneken, Narendra V. Shenoy
    Discrete Drive Selection for Continuous Sizing. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:110-115 [Conf]
  20. Stan Y. Liao, Narendra V. Shenoy, William Nicholls
    An Efficient External-Memory Implementation of Region Query with Application to Area Routing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:36-41 [Conf]
  21. Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Retiming of Circuits with Single Phase Transparent Latches. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:86-89 [Conf]
  22. Narendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking
    A Robust Solution to the Timing Convergence Problem in High-Performance Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:250-257 [Conf]
  23. Kurt Keutzer, A. Richard Newton, Narendra V. Shenoy
    The future of logic synthesis and physical design in deep-submicron process geometries. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:218-224 [Conf]
  24. Debjit Sinha, Hai Zhou, Narendra V. Shenoy
    Advances in Computation of the Maximum of a Set of Random Variables. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:306-311 [Conf]
  25. Shabbir H. Batterywala, Narendra V. Shenoy
    A Method to Estimate Slew and Delay in Coupled Digital Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:411-416 [Conf]
  26. Shabbir H. Batterywala, Narendra V. Shenoy
    Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:989-994 [Conf]
  27. Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Functional clock schedule optimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:93-98 [Conf]
  28. Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou
    Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:875-880 [Conf]
  29. Narendra V. Shenoy
    Retiming: Theory and practice. [Citation Graph (0, 0)][DBLP]
    Integration, 1997, v:22, n:1-2, pp:1-21 [Journal]
  30. Hai Zhou, Narendra V. Shenoy, William Nicholls
    Efficient minimum spanning tree construction without Delaunay triangulation. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 2002, v:81, n:5, pp:271-276 [Journal]
  31. Debjit Sinha, Narendra V. Shenoy, Hai Zhou
    Statistical Timing Yield Optimization by Gate Sizing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:10, pp:1140-1146 [Journal]

  32. On Efficient and Robust Constraint Generation for Practical Layout Legalization. [Citation Graph (, )][DBLP]


  33. Cell Swapping Based Migration Methodology for Analog and Custom Layouts. [Citation Graph (, )][DBLP]


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