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Publications of Author

1. Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton
   Efficient static timing analysis using a unified framework for false paths and multi-cycle paths. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2006, pp:73-78 [Conf]
   
2. Michael Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo
   A methodology for FPGA to structured-ASIC synthesis and verification. [Citation Graph (0, 0)][DBLP]
   DATE Designers' Forum, 2006, pp:64-69 [Conf]
   
3. Michael Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh Patel, Bruce Pedersen, Jay Schleicher, Sergey Shumarayev
   Interconnect enhancements for a high-speed PLD architecture. [Citation Graph (0, 0)][DBLP]
   FPGA, 2002, pp:3-10 [Conf]
   
4. Michael Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini
   Improving FPGA Performance and Area Using an Adaptive Logic Module. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:135-144 [Conf]
   
5. Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris
   Improving the efficiency of static timing analysis with false paths. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:527-531 [Conf]