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Chaitali Chakrabarti: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jianli Zhuo, Chaitali Chakrabarti
    An efficient dynamic task scheduling algorithm for battery powered DVS systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:846-849 [Conf]
  2. Youngjin Cho, Naehyuck Chang, Chaitali Chakrabarti, Sarma B. K. Vrudhula
    High-level power management of embedded systems with application-specific energy cost functions. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:568-573 [Conf]
  3. Daler N. Rakhmatov, Sarma B. K. Vrudhula, Chaitali Chakrabarti
    Battery-conscious task sequencing for portable devices including voltage/clock scaling. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:189-194 [Conf]
  4. Wen-Tsong Shiue, Chaitali Chakrabarti
    Memory Exploration for Low Power, Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:140-145 [Conf]
  5. Sathishkumar Udayanarayanan, Chaitali Chakrabarti
    Address Code Generation for Digital Signal Processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:353-358 [Conf]
  6. Jianli Zhuo, Chaitali Chakrabarti
    System-level energy-efficient dynamic task scheduling. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:628-631 [Conf]
  7. Jianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula
    Extending the lifetime of fuel cell based hybrid systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:562-567 [Conf]
  8. Rusell E. Henning, Chaitali Chakrabarti
    High-Level Design Synthesis of a Low Power, VLIW Processor for the IS-54 VSELP Speech Encoder. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:571-576 [Conf]
  9. Ali Manzak, Chaitali Chakrabarti
    Voltage Scaling for Energy Minimization with QoS Constraints. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:438-446 [Conf]
  10. Kala Srivatsan, Chaitali Chakrabarti, Lori Lucke
    Low power data format converter design using semi-static register allocation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:460-465 [Conf]
  11. Kishore Andra, Tinku Acharya, Chaitali Chakrabarti
    A Multi-Bit Binary Arithmetic Coding Technique. [Citation Graph (0, 0)][DBLP]
    ICIP, 2000, pp:- [Conf]
  12. Chaitali Chakrabarti, Lori Lucke
    Efficient Architectures for Hidden Surface Removal. [Citation Graph (0, 0)][DBLP]
    ICIP (1), 1994, pp:661-665 [Conf]
  13. Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner
    SODA: A Low-power Architecture For Software Radio. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:89-101 [Conf]
  14. Chaitali Chakrabarti
    Efficient stack filter implementations of rank order filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:958-961 [Conf]
  15. Chaitali Chakrabarti, Li-Yu Wang
    Novel Sorting Netowrk-Based Architectures for Rank Order Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:89-93 [Conf]
  16. Gagan Gupta, Chaitali Chakrabarti
    VLSI Architectures for Hierarchical Block Matching. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:215-218 [Conf]
  17. Srikanth Karkada, Chaitali Chakrabarti, Andreas Spanias
    High Sample Rate Architectures for Block Adaptive Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:131-134 [Conf]
  18. Hsiang-Ling Li, Chaitali Chakrabarti
    A New Viterbi Decoder Design for Code Rate K/N. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:549-552 [Conf]
  19. Lori Lucke, Chaitali Chakrabarti
    A Digit-Serial Architecture for Gray-Scale Morphological Filtering. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:207-210 [Conf]
  20. Ali Manzak, Chaitali Chakrabarti
    A low power scheduling scheme with resources operating at multiple voltages. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:354-357 [Conf]
  21. Wen-Tsong Shiue, Chaitali Chakrabarti
    Memory exploration for low power embedded systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:250-253 [Conf]
  22. Jameel Ahmed, Chaitali Chakrabarti
    A dynamic task scheduling algorithm for battery powered DVS systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:813-816 [Conf]
  23. Hafijur Rahman, Chaitali Chakrabarti
    A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:297-300 [Conf]
  24. Sumant Bhutoria, Chaitali Chakrabarti
    Parameterized SoC design for portable systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:449-452 [Conf]
  25. Kishore Andra, Chaitali Chakrabarti, Tinku Acharya
    A high performance JPEG2000 architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:765-768 [Conf]
  26. Rusell E. Henning, Chaitali Chakrabarti
    Low-power approach for decoding convolutional codes with adaptive viterbi algorithm approximations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:68-71 [Conf]
  27. Ali Manzak, Chaitali Chakrabarti
    Variable voltage task scheduling algorithms for minimizing energy. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:279-282 [Conf]
  28. Sathishkumar Udayanarayanan, Chaitali Chakrabarti
    Energy-efficient code generation for DSP56000 family (poster session). [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:247-249 [Conf]
  29. Hyunseok Lee, Trevor N. Mudge, Chaitali Chakrabarti
    Reducing idle mode power in software defined radio terminals. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:101-106 [Conf]
  30. Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Chakrabarti, Naehyuck Chang
    An optimal analytical solution for processor speed control with thermal constraints. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:292-297 [Conf]
  31. Jianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula
    Maximizing the lifetime of embedded systems powered by fuel cell-battery hybrids. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:424-429 [Conf]
  32. Ali Manzak, Chaitali Chakrabarti
    Optimum Buffer Size for Dynamic Voltage Processors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:711-721 [Conf]
  33. Russell Henning, Chaitali Chakrabarti
    Relating Data Characteristics to Transition Activity in High-Level Static CMOS Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:38-43 [Conf]
  34. Todd M. Austin, David Blaauw, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Wayne Wolf
    Mobile Supercomputers. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2004, v:37, n:5, pp:81-83 [Journal]
  35. Hsiang-Ling Li, Chaitali Chakrabarti
    Motion estimation of two-dimensional objects based on the straight line hough transform: A new approach. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 1996, v:29, n:8, pp:1245-1258 [Journal]
  36. Rahim Khoja, Mehul Marolia, Tinku Acharya, Chaitali Chakrabarti
    A coprocessor architecture for fast protein structure prediction. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 2006, v:39, n:12, pp:2494-2505 [Journal]
  37. Chaitali Chakrabarti, Joseph JáJá
    Systolic Architectures for the Computation of the Discrete Hartley and the Discrete Cosine Transforms Based on Prime Factor Decomposition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:11, pp:1359-1368 [Journal]
  38. Chaitali Chakrabarti, Joseph JáJá
    VLSI Architectures for Multidimensional Transforms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:9, pp:1053-1057 [Journal]
  39. Kishore Andra, Chaitali Chakrabarti, Tinku Acharya
    A high-performance JPEG2000 architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2003, v:13, n:3, pp:209-0 [Journal]
  40. Lori Lucke, Chaitali Chakrabarti
    A digit-serial architecture for gray-scale morphological filtering. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Image Processing, 1995, v:4, n:3, pp:387-391 [Journal]
  41. Wen-Tsong Shiue, Sathishkumar Udayanarayanan, Chaitali Chakrabarti
    Data memory design and exploration for low-power embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:4, pp:553-568 [Journal]
  42. Chaitali Chakrabarti, Lori E. Lucke
    VLSI architectures for weighted order statistic (WOS) filters. [Citation Graph (0, 0)][DBLP]
    Signal Processing, 2000, v:80, n:8, pp:1419-1433 [Journal]
  43. Jianli Zhuo, Chaitali Chakrabarti, Kyungsoo Lee, Naehyuck Chang
    Dynamic Power Management with Hybrid Power Sources. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:871-876 [Conf]
  44. Mark Woh, Sangwon Seo, Hyunseok Lee, Yuan Lin, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner
    The Next Generation Challenge for Software Defined Radio. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:343-354 [Conf]
  45. Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner
    SODA: A High-Performance DSP Architecture for Software-Defined Radio. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:1, pp:114-123 [Journal]
  46. Ye Li, Bertan Bakkaloglu, Chaitali Chakrabarti
    A System Level Energy Model and Energy-Quality Evaluation for Integrated Transceiver Front-Ends. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:90-103 [Journal]
  47. Chaitali Chakrabarti, Li-Yu Wang
    Novel sorting network-based architectures for rank order filters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:502-507 [Journal]
  48. Ali Manzak, Chaitali Chakrabarti
    Variable voltage task scheduling algorithms for minimizing energy/power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:270-276 [Journal]
  49. Tinku Acharya, Chaitali Chakrabarti
    A Survey on Lifting-based Discrete Wavelet Transform Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:42, n:3, pp:321-339 [Journal]

  50. Energy-aware error control coding for Flash memories. [Citation Graph (, )][DBLP]


  51. A special-purpose compiler for look-up table and code generation for function evaluation. [Citation Graph (, )][DBLP]


  52. TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms. [Citation Graph (, )][DBLP]


  53. Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering. [Citation Graph (, )][DBLP]


  54. An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities. [Citation Graph (, )][DBLP]


  55. AnySP: anytime anywhere anyway signal processing. [Citation Graph (, )][DBLP]


  56. Energy management of DVS-DPM enabled embedded systems powered by fuel cell-battery hybrid source. [Citation Graph (, )][DBLP]


  57. Extending the lifetime of media recorders constrained by battery and flash memory size. [Citation Graph (, )][DBLP]


  58. Throughput of multi-core processors under thermal constraints. [Citation Graph (, )][DBLP]


  59. Low power robust signal processing. [Citation Graph (, )][DBLP]


  60. Diet SODA: a power-efficient processor for digital cameras. [Citation Graph (, )][DBLP]


  61. From SODA to scotch: The evolution of a wireless baseband processor. [Citation Graph (, )][DBLP]


  62. A parameterized dataflow language extension for embedded streaming systems. [Citation Graph (, )][DBLP]


  63. Customizing wide-SIMD architectures for H.264. [Citation Graph (, )][DBLP]


  64. Sphere Decoding for Multiprocessor Architectures. [Citation Graph (, )][DBLP]


  65. Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations. [Citation Graph (, )][DBLP]


  66. Design and Analysis of LDPC Decoders for Software Defined Radio. [Citation Graph (, )][DBLP]


  67. Efficient image reconstruction using partial 2D Fourier transform. [Citation Graph (, )][DBLP]


  68. Efficient mapping of advanced signal processing algorithms on multi-processor architectures. [Citation Graph (, )][DBLP]


  69. Architecture-Aware LDPC Code Design for Software Defined Radio. [Citation Graph (, )][DBLP]


  70. Design and Implementation of Turbo Decoders for Software Defined Radio. [Citation Graph (, )][DBLP]


  71. FPGA architecture for 2D Discrete Fourier Transform based on 2D decomposition for large-sized data. [Citation Graph (, )][DBLP]


  72. Accurate models for estimating area and power of FPGA implementations. [Citation Graph (, )][DBLP]


  73. Mobile Supercomputers for the Next-Generation Cell Phone. [Citation Graph (, )][DBLP]


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