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Publications of Author

1. Sudhir Ahuja, Abhaya Asthana
   A Multi-Microprocessor Architecture with Hardware Support for Communication and Scheduling. [Citation Graph (1, 0)][DBLP]
   ASPLOS, 1982, pp:205-209 [Conf]
   
2. Abhaya Asthana, H. V. Jagadish, Scott C. Knauer
   An Intelligent Memory Transaction Engine. [Citation Graph (1, 0)][DBLP]
   IWDM, 1989, pp:286-300 [Conf]
   
3. Nandit Soparkar, Paul Krzyzanowski, H. V. Jagadish, Abhaya Asthana
   Run-Time Parallelization of Sequential Database Programs. [Citation Graph (0, 3)][DBLP]
   CIKM, 1995, pp:74-81 [Conf]
   
4. Abhaya Asthana, H. V. Jagadish, Paul Krzyzanowski
   The Design of a Back-end Object Management System. [Citation Graph (0, 0)][DBLP]
   Code Generation, 1991, pp:294-319 [Conf]
   
5. Abhaya Asthana, Boyd Mathews, Cheryl J. Briggs, Mark R. Cravats
   A VLSI Building Block for Massively Parallel Computation. [Citation Graph (0, 0)][DBLP]
   FGCS, 1988, pp:879-886 [Conf]
   
6. Abhaya Asthana, Mark Cravatts, Paul Krzyzanowski
   An Experimental Active-Memory-Based Network Environment. [Citation Graph (0, 0)][DBLP]
   HPDC, 1994, pp:139-146 [Conf]
   
7. Abhaya Asthana, James Sienicki, Mani B. Srivastava
   Kaleido: An Environment for Composing Networked Multimedia Applications. [Citation Graph (0, 0)][DBLP]
   HPDC, 1997, pp:181-190 [Conf]
   
8. Abhaya Asthana, H. V. Jagadish, Boyd Mathews
   Impact of Advanced VLSI Packaging on the Design of a Large Parallel Computer. [Citation Graph (0, 0)][DBLP]
   ICPP (1), 1989, pp:323-327 [Conf]
   
9. Abhaya Asthana, Cheryl J. Briggs, Mark R. Cravats, Boyd Mathews
   The Architecture of Massively Parallel Numeric Processor. [Citation Graph (0, 0)][DBLP]
   IFIP Congress, 1989, pp:891-891 [Conf]
   
10. Abhaya Asthana, Mark Cravatts, Paul Krzyzanowski
    SWIM Active Memory: Architecture and Applications. [Citation Graph (0, 0)][DBLP]
    IFIP Congress (1), 1994, pp:183-188 [Conf]
    
11. Abhaya Asthana, Mark Cravatts, Paul Krzyzanowski
    Towards a Programming Environment for a Computer with Intelligent Memory. [Citation Graph (0, 0)][DBLP]
    IFIP PACT, 1994, pp:89-98 [Conf]
    
12. Abhaya Asthana, Paul Krzyzanowski
    A Memory Participative Architecture for High Performance Communication Systems. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 1994, pp:167-174 [Conf]
    
13. J. A. Chandross, H. V. Jagadish, Abhaya Asthana
    The trap as a control flow mechanism. [Citation Graph (0, 0)][DBLP]
    MICRO, 1988, pp:50-52 [Conf]
    
14. Abhaya Asthana, Mike Laznovsky, Boyd Mathews
    SEMU: A Parallel Processing System for Timing Simulation of Digital CMOS VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:33-38 [Conf]
    
15. Harvey I. Epstein, Abhaya Asthana, Stephen A. Corum, Leen Mak
    Hybrid network management. [Citation Graph (0, 0)][DBLP]
    Bell Labs Technical Journal, 2000, v:5, n:4, pp:63-79 [Journal]
    
16. Abhaya Asthana, Eric J. Bauer, Meenakshi Sharma, Xuemei Zhang
    End-to-end availability considerations for services over IMS. [Citation Graph (0, 0)][DBLP]
    Bell Labs Technical Journal, 2006, v:11, n:3, pp:199-210 [Journal]
    
17. Bernard L. Malone III, Abhaya Asthana
    Analyzing network availability of a mobile data network: A case study. [Citation Graph (0, 0)][DBLP]
    Bell Labs Technical Journal, 2006, v:11, n:3, pp:47-56 [Journal]
    
18. Abhaya Asthana
    Design and Control of a Three-Stage Switch Matrix in the Presence of Fan-Out. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:10, pp:886-895 [Journal]
    
19. 
    Logic-enhanced memory for high performance databases. [Citation Graph (, )][DBLP]