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Sergei Y. Larin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chao-ying Fu, Matthew D. Jennings, Sergei Y. Larin, Thomas M. Conte
    Value Speculation Scheduling for High Performance Processors. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1998, pp:262-271 [Conf]
  2. Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye
    Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:201-211 [Conf]
  3. Sergei Y. Larin, Thomas M. Conte
    Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:82-92 [Conf]

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