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William Y. Chen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. David M. Gallagher, William Y. Chen, Scott A. Mahlke, John C. Gyllenhaal, Wen-mei W. Hwu
    Dynamic Memory Disambiguation Using the Memory Conflict Buffer. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1994, pp:183-193 [Conf]
  2. Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker
    Sentinel Scheduling for VLIW and Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1992, pp:238-247 [Conf]
  3. William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu
    Tolerating First Level Memory Access Latency in High-Performance Systems. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1992, pp:36-43 [Conf]
  4. Scott A. Mahlke, Nancy J. Warter, William Y. Chen, Pohua P. Chang, Wen-mei W. Hwu
    The Effect of Compiler Optimizations on Available Parallelism in Scalar Programs. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1991, pp:142-145 [Conf]
  5. William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu, Tokuzo Kiyohara, Pohua P. Chang
    Tolerating data access latency with register preloading. [Citation Graph (0, 0)][DBLP]
    ICS, 1992, pp:104-113 [Conf]
  6. Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu
    IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:266-275 [Conf]
  7. Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu
    IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:408-417 [Conf]
  8. Tokuzo Kiyohara, Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Sadun Anik, Wen-mei W. Hwu
    Register Connection: A New Approach to Adding Registers into Instruction Set Architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:247-256 [Conf]
  9. William Y. Chen, Roger A. Bringmann, Scott A. Mahlke, Sadun Anik, Tokuzo Kiyohara, Nancy J. Warter, Daniel M. Lavery, Wen-mei W. Hwu, Richard E. Hank, John C. Gyllenhaal
    Using Profile Information to Assist Advaced Compiler Optimization and Scheduling. [Citation Graph (0, 0)][DBLP]
    LCPC, 1992, pp:31-48 [Conf]
  10. Pohua P. Chang, William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu
    Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:25-33 [Conf]
  11. William Y. Chen, Roger A. Bringmann, Scott A. Mahlke, Richard E. Hank, James E. Sicolo
    An efficient architecture for loop based data preloading. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:92-101 [Conf]
  12. William Y. Chen, Scott A. Mahlke, Pohua P. Chang, Wen-mei W. Hwu
    Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:69-73 [Conf]
  13. Scott A. Mahlke, David C. Lin, William Y. Chen, Richard E. Hank, Roger A. Bringmann
    Effective compiler support for predicated execution using the hyperblock. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:45-54 [Conf]
  14. Scott A. Mahlke, William Y. Chen, John C. Gyllenhaal, Wen-mei W. Hwu
    Compiler Code Transformations for Superscalar-Based High Performance Systems. [Citation Graph (0, 0)][DBLP]
    SC, 1992, pp:808-817 [Conf]
  15. Jay Bharadwaj, William Y. Chen, Weihaw Chuang, Gerolf Hoflehner, Kishore N. Menezes, Kalyan Muthukumar, Jim Pierce
    The Intel IA-64 Compiler Code Generator. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2000, v:20, n:5, pp:44-53 [Journal]
  16. Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu
    Profile-guided Automatic Inline Expansion for C Programs. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1992, v:22, n:5, pp:349-369 [Journal]
  17. Pohua P. Chang, Daniel M. Lavery, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu
    The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:3, pp:353-370 [Journal]
  18. Pohua P. Chang, Nancy J. Warter, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu
    Three Architecutral Models for Compiler-Controlled Speculative Execution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:4, pp:481-494 [Journal]
  19. William Y. Chen, Pohua P. Chang, Thomas M. Conte, Wen-mei W. Hwu
    The Effect of Code Expanding Optimizations on Instruction Cache Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:9, pp:1045-1057 [Journal]
  20. Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker
    Sentinel Scheduling for VLIW and Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 1993, v:11, n:4, pp:376-408 [Journal]

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