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Michael D. Powell: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mohamed Gomaa, Michael D. Powell, T. N. Vijaykumar
    Heat-and-run: leveraging SMT and CMP to manage power density through the operating system. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2004, pp:260-270 [Conf]
  2. Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar
    An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:147-158 [Conf]
  3. Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T. N. Vijaykumar
    Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:151-0 [Conf]
  4. Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar
    Optimizing Replication, Communication, and Capacity Allocation in CMPs. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:357-368 [Conf]
  5. Michael D. Powell, T. N. Vijaykumar
    Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:72-83 [Conf]
  6. Michael D. Powell, T. N. Vijaykumar
    Exploiting Resonant Behavior to Reduce Inductive Noise. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:288-301 [Conf]
  7. Michael D. Powell, T. N. Vijaykumar
    Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:223-228 [Conf]
  8. Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar
    Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:55-66 [Conf]
  9. Il Park, Michael D. Powell, T. N. Vijaykumar
    Reducing register ports for higher speed and lower energy. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:171-182 [Conf]
  10. Michael D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy
    Reducing set-associative cache energy via way-prediction and selective direct-mapping. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:54-65 [Conf]
  11. Michael D. Powell, Ethan Schuchman, T. N. Vijaykumar
    Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:294-304 [Conf]
  12. Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, N. Vijaykumar
    Reducing leakage in a high-performance deep-submicron instruction cache. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:77-89 [Journal]

  13. CAMP: A technique to estimate per-structure power at run-time using a few simple parameters. [Citation Graph (, )][DBLP]

  14. Architectural core salvaging in a multi-core processor for hard-error tolerance. [Citation Graph (, )][DBLP]

  15. Resource area dilation to reduce power density in throughput servers. [Citation Graph (, )][DBLP]

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