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James R. Goodman: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. James R. Goodman, Carlo H. Séquin
    Hypertree: A Multiprocessor Interconnection Topology. [Citation Graph (3, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:12, pp:923-933 [Journal]
  2. James R. Goodman
    Using Cache Memory to Reduce Processor-Memory Traffic [Citation Graph (1, 0)][DBLP]
    ISCA, 1983, pp:124-131 [Conf]
  3. James R. Goodman, Philip J. Woest
    The Wisconsin Multicube: A New Large-Scale Cache-Coherent Multiprocessor. [Citation Graph (1, 0)][DBLP]
    ISCA, 1988, pp:422-431 [Conf]
  4. Steven L. Scott, James R. Goodman, Mary K. Vernon
    Performance of the SCI Ring. [Citation Graph (1, 0)][DBLP]
    ISCA, 1992, pp:403-414 [Conf]
  5. James R. Goodman
    Coherency for Multiprocessor Virtual Address Caches. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1987, pp:72-81 [Conf]
  6. James R. Goodman, Mary K. Vernon, Philip J. Woest
    Efficent Synchronization Primitives for Large-Scale Cache-Coherent Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1989, pp:64-75 [Conf]
  7. Ravi Rajwar, James R. Goodman
    Transactional lock-free execution of lock-based programs. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2002, pp:5-17 [Conf]
  8. Chinya V. Ravishankar, James R. Goodman
    VLSI Considerations that Influence Data Flow Architecture. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1982, pp:228-232 [Conf]
  9. Stefanos Kaxiras, James R. Goodman
    Improving CC-NUMA Performance Using Instruction-Based Prediction. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:161-0 [Conf]
  10. Ravi Rajwar, Alain Kägi, James R. Goodman
    Improving the Throughput of Synchronization by Insertion of Delays. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:168-0 [Conf]
  11. Ross E. Johnson, James R. Goodman
    Synthesizing General Topologies from Rings. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1992, pp:86-95 [Conf]
  12. Honesty C. Young, James R. Goodman
    The Design of a Queue-Based Vector Supercomputer. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:483-486 [Conf]
  13. James R. Goodman, Wei-Chung Hsu
    Code scheduling and register allocation in large basic blocks. [Citation Graph (0, 0)][DBLP]
    ICS, 1988, pp:442-452 [Conf]
  14. Stefanos Kaxiras, James R. Goodman
    The GLOW Cache Coherence Protocol Extensions for Widely Shared Data. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1996, pp:35-43 [Conf]
  15. Stefanos Kaxiras, Stein Gjessing, James R. Goodman
    A Study of Three Dynamic Approaches to Handle Widely Shared Data in Shared-memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:457-464 [Conf]
  16. Alain Kägi, Nagi Aboulenein, Doug Burger, James R. Goodman
    Techniques for Reducing Overheads of Shared-Memory Multiprocessing. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1995, pp:11-20 [Conf]
  17. Ravi Rajwar, Alain Kägi, James R. Goodman
    Inferential queueing and speculative push for reducing critical communication latencies. [Citation Graph (0, 0)][DBLP]
    ICS, 2003, pp:273-284 [Conf]
  18. Gurindar S. Sohi, James E. Smith, James R. Goodman
    Restricted Fetch&Phi operations for parallel processing. [Citation Graph (0, 0)][DBLP]
    ICS, 1989, pp:410-416 [Conf]
  19. Nagi Aboulenein, James R. Goodman, Stein Gjessing, Philip J. Woest
    Hardware Support for Synchronization in the Scalable Coherent Interface (SCI). [Citation Graph (0, 0)][DBLP]
    IPPS, 1994, pp:141-150 [Conf]
  20. Doug Burger, James R. Goodman, Alain Kägi
    Memory Bandwidth Limitations of Future Microprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:78-89 [Conf]
  21. Doug Burger, Stefanos Kaxiras, James R. Goodman
    DataScalar Architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:338-349 [Conf]
  22. James R. Goodman
    Retrospective: Using Cache Memory to Reduce Processor-Memory Traffic. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:32-33 [Conf]
  23. James R. Goodman
    Using Cache Memory to Reduce Processor-Memory Traffic. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:255-262 [Conf]
  24. James R. Goodman, MenChow Chiang
    The Use of Static Column RAM as a Memory Hierarchy. [Citation Graph (0, 0)][DBLP]
    ISCA, 1984, pp:167-174 [Conf]
  25. James R. Goodman, Wei-Chung Hsu
    On the Use of Registers vs. Cache to Minimize Memory Traffic. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:375-383 [Conf]
  26. James R. Goodman, Jian-tu Hsieh, Koujuch Liou, Andrew R. Pleszkun, P. B. Schechter, Honesty C. Young
    PIPE: A VLSI Decoupled Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1985, pp:20-27 [Conf]
  27. Alain Kägi, Doug Burger, James R. Goodman
    Efficient Synchronization: Let Them Eat QOLB. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:170-180 [Conf]
  28. Andrew R. Pleszkun, James R. Goodman, Wei-Chung Hsu, R. T. Joersz, George E. Bier, Philip J. Woest, P. B. Schechter
    WISQ: A Restartable Architecture Using Queues. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:290-299 [Conf]
  29. James E. Smith, James R. Goodman
    A Study of Instruction Cache Organizations and Replacement Policies [Citation Graph (0, 0)][DBLP]
    ISCA, 1983, pp:132-137 [Conf]
  30. Ravi Rajwar, James R. Goodman
    Speculative lock elision: enabling highly concurrent multithreaded execution. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:294-305 [Conf]
  31. Doug Burger, James R. Goodman
    Billion-Transistor Architectures: There and Back Again. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2004, v:37, n:3, pp:22-28 [Journal]
  32. Doug Burger, James R. Goodman
    Billion-Transistor Architectures - Guest Editors' Introduction. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:9, pp:46-49 [Journal]
  33. Ravi Rajwar, Alain Kägi, James R. Goodman
    Inferential Queueing and Speculative Push. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2004, v:32, n:3, pp:225-258 [Journal]
  34. Howard Jay Siegel, Seth Abraham, William L. Bain, Kenneth E. Batcher, Thomas L. Casavant, Doug DeGroot, Jack B. Dennis, David C. Douglas, Tse-Yun Feng, James R. Goodman, Alan Huang, Harry F. Jordan, J. Robert Jamp, Yale N. Patt, Alan Jay Smith, James E. Smith, Lawrence Snyder, Harold S. Stone, Russ Tuck, Benjamin W. Wah
    Report of the Purdue Workshop on Grand Challenges in Computer Architecture for the Support of High Performance Computing. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1992, v:16, n:3, pp:199-211 [Journal]
  35. James R. Goodman, Honesty C. Young
    Comments on ``A Massive Memory Machine''. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:10, pp:907-910 [Journal]
  36. James E. Smith, James R. Goodman
    Instruction Cache Replacement Policies and Organizations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:3, pp:234-241 [Journal]
  37. Steven L. Scott, James R. Goodman
    Performance of Pruning-Cache Directories for Large-Scale Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1993, v:4, n:5, pp:520-534 [Journal]
  38. Steven L. Scott, James R. Goodman
    The Impact of Pipelined Channels on k-ary n-Cube Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1994, v:5, n:1, pp:2-16 [Journal]
  39. Wei-Chung Hsu, Charles N. Fischer, James R. Goodman
    On the Minimization of Loads/Stores in Local Register Allocation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1989, v:15, n:10, pp:1252-1260 [Journal]

  40. NZTM: nonblocking zero-indirection transactional memory. [Citation Graph (, )][DBLP]


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