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Alessandro Forin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. David B. Golub, Randall W. Dean, Alessandro Forin, Richard F. Rashid
    UNIX as an Application Program. [Citation Graph (1, 0)][DBLP]
    USENIX Summer, 1990, pp:87-95 [Conf]
  2. Roberto Bisiani, Alessandro Forin
    Architectural Support for Multilanguage Parallel Programming on Heterogeneous Systems. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1987, pp:21-30 [Conf]
  3. Roberto Bisiani, Alessandro Forin
    Multilanguage Parallel Programming. [Citation Graph (0, 0)][DBLP]
    ICPP, 1987, pp:381-384 [Conf]
  4. Alessandro Forin, David B. Golub, Brian N. Bershad
    An I/O System for Mach 3.0. [Citation Graph (0, 0)][DBLP]
    USENIX MACH Symposium, 1991, pp:163-176 [Conf]
  5. Alessandro Forin
    Debugging of Heterogeneous Parallel Systems. [Citation Graph (0, 0)][DBLP]
    Workshop on Parallel and Distributed Debugging, 1988, pp:130-140 [Conf]
  6. Johannes Helander, Alessandro Forin
    MMLite: a highly componentized system architecture. [Citation Graph (0, 0)][DBLP]
    ACM SIGOPS European Workshop, 1998, pp:96-103 [Conf]
  7. Michael B. Jones, Daniel L. McCulley, Alessandro Forin, Paul J. Leach, Daniela Rosu, Daniel L. Roberts
    An overview of the Rialto real-time architecture. [Citation Graph (0, 0)][DBLP]
    ACM SIGOPS European Workshop, 1996, pp:249-256 [Conf]
  8. Alessandro Forin, Gerald R. Malan
    An MS-DOS Filesystem for UNIX. [Citation Graph (0, 0)][DBLP]
    USENIX Winter, 1994, pp:337-354 [Conf]
  9. Roberto Bisiani, Alessandro Forin
    Multilanguage Parallel Programming of Heterogeneous Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:8, pp:930-945 [Journal]
  10. Ping Hang Cheung, Alessandro Forin
    A C-Language Binding for PSL. [Citation Graph (0, 0)][DBLP]
    ICESS, 2007, pp:584-591 [Conf]

  11. Scalable specification mining for verification and diagnosis. [Citation Graph (, )][DBLP]

  12. Path-based scheduling in a hardware compiler. [Citation Graph (, )][DBLP]

  13. Lost in Space! Quantifying the Elements of FPGA Speedup. [Citation Graph (, )][DBLP]

  14. Hardware Compilation from Machine Code with M2V. [Citation Graph (, )][DBLP]

  15. An Extensible I/O Subsystem. [Citation Graph (, )][DBLP]

  16. Combining multicore and reconfigurable instruction set extensions. [Citation Graph (, )][DBLP]

  17. Minimizing partial reconfiguration overhead with fully streaming DMA engines and intelligent ICAP controller (abstract only). [Citation Graph (, )][DBLP]

  18. Automatic bus macro placement for partially reconfigurable FPGA designs. [Citation Graph (, )][DBLP]

  19. Energy reduction with run-time partial reconfiguration (abstract only). [Citation Graph (, )][DBLP]

  20. Reconfigurable custom floating-point instructions (abstract only). [Citation Graph (, )][DBLP]

  21. Exploiting partial reconfiguration for flexible software debugging. [Citation Graph (, )][DBLP]

  22. Extensible On-Chip Peripherals. [Citation Graph (, )][DBLP]

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