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Nicholas P. Carter: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Nicholas P. Carter, Stephen W. Keckler, William J. Dally
    Hardware Support for Fast Capability-based Addressing. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1994, pp:319-327 [Conf]
  2. Jeffrey J. Cook, Derek B. Gottlieb, Joshua D. Walstrom, Steve Ferrera, Chi-Wei Wang, Nicholas P. Carter
    Mapping Algorithms to the Amalgam Programmable-Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:311-0 [Conf]
  3. Joshua D. Walstrom, Jeffrey J. Cook, Derek B. Gottlieb, Steve Ferrera, Chi-Wei Wang, Nicholas P. Carter
    The Design of the Amalgam Reconfigurable Cluster. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:309-310 [Conf]
  4. Steve Ferrera, Nicholas P. Carter
    A magnetoelectronic macrocell employing reconfigurable threshold logic. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:143-151 [Conf]
  5. Richard B. Kujoth, Chi-Wei Wang, Derek B. Gottlieb, Jeffrey J. Cook, Nicholas P. Carter
    A reconfigurable unit for a clustered programmable-reconfigurable processor. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:200-209 [Conf]
  6. Steve Ferrera, Nicholas P. Carter
    Reconfigurable Circuits Using Hybrid Hall Effect Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1-10 [Conf]
  7. Chi-Wei Wang, Nicholas P. Carter, Richard B. Kujoth, Jeffrey J. Cook, Derek B. Gottlieb
    Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:57-64 [Conf]
  8. Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang, Whay Sing Lee
    Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:306-317 [Conf]
  9. Nicholas P. Carter, William J. Dally, Whay Sing Lee, Stephen W. Keckler, Andrew Chang
    Processor Mechanisms for Software Shared Memory. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2000, pp:120-133 [Conf]
  10. Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter, Andrew Chang, Yevgeny Gurevich, Whay Sing Lee
    The M-Machine multicomputer. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:146-156 [Conf]
  11. Derek B. Gottlieb, Nicholas P. Carter
    Microprocessor Interfacing Laboratory. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:106-107 [Conf]
  12. Whay Sing Lee, William J. Dally, Stephen W. Keckler, Nicholas P. Carter, Andrew Chang
    An Efficient, Protected Message Interface. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1998, v:31, n:11, pp:69-75 [Journal]
  13. Nicholas P. Carter, Azmat Hussain
    Modeling wire delay, area, power, and performance in a simulation infrastructure. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2006, v:50, n:2-3, pp:311-320 [Journal]
  14. Love Kothari, Nicholas P. Carter
    Architecture of a Self-Checkpointing Microprocessor that Incorporates Nanomagnetic Devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:2, pp:161-173 [Journal]
  15. Richard B. Kujoth, Chi-Wei Wang, Jeffrey J. Cook, Derek B. Gottlieb, Nicholas P. Carter
    A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:2, pp:146-159 [Journal]
  16. Pratyush Das Kanungo, Alexandra Imre, Wu Bin, Alexei O. Orlov, Gregory L. Snider, Wolfgang Porod, Nicholas P. Carter
    Gated hybrid Hall effect device on silicon. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2005, v:36, n:3-6, pp:294-297 [Journal]

  17. Design techniques for cross-layer resilience. [Citation Graph (, )][DBLP]


  18. Vision for cross-layer optimization to address the dual challenges of energy and reliability. [Citation Graph (, )][DBLP]


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