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Publications of Author

1. Mark Holland, Garth A. Gibson
   Parity Declustering for Continuous Operation in Redundant Disk Arrays. [Citation Graph (11, 0)][DBLP]
   ASPLOS, 1992, pp:23-35 [Conf]
   
2. Daniel Stodolsky, Garth A. Gibson, Mark Holland
   Parity Logging Overcoming the Small Write Problem in Redundant Disk Arrays. [Citation Graph (9, 0)][DBLP]
   ISCA, 1993, pp:64-75 [Conf]
   
3. Mark Holland, Garth A. Gibson, Daniel P. Siewiorek
   Fast, On-Line Failure Recovery in Redundant Disk Arrays. [Citation Graph (2, 0)][DBLP]
   FTCS, 1993, pp:422-431 [Conf]
   
4. Mark Holland, Garth A. Gibson, Daniel P. Siewiorek
   Architectures and Algorithms for On-Line Failure Recovery in Redundant Disk Arrays. [Citation Graph (2, 0)][DBLP]
   Distributed and Parallel Databases, 1994, v:2, n:3, pp:295-335 [Journal]
   
5. Garth A. Gibson, Daniel Stodolsky, Fay W. Chang, William V. Courtright II, Chris G. Demetriou, Eka Ginting, Mark Holland, Qingming Ma, LeAnn Neal, R. Hugo Patterson, Jiawen Su, Rachad Youssef, Jim Zelenka
   The Scotch Parallel Storage Systems. [Citation Graph (1, 0)][DBLP]
   COMPCON, 1995, pp:403-410 [Conf]
   
6. Daniel Stodolsky, Mark Holland, William V. Courtright II, Garth A. Gibson
   Parity-Logging Disk Arrays. [Citation Graph (1, 0)][DBLP]
   ACM Trans. Comput. Syst., 1994, v:12, n:3, pp:206-235 [Journal]
   
7. Mark Holland, Scott Hauck
   Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC. [Citation Graph (0, 0)][DBLP]
   FCCM, 2005, pp:289-290 [Conf]
   
8. Mark Holland, Scott Hauck
   Improving performance and robustness of domain-specific CPLDs. [Citation Graph (0, 0)][DBLP]
   FPGA, 2006, pp:50-59 [Conf]
   
9. Mark Holland, Scott Hauck
   Automatic Creation of Reconfigurable PALs/PLAs for SoC. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:536-545 [Conf]
   
10. Mark Holland, Scott Hauck
    Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:95-100 [Conf]
    
11. Mark Holland, James Harris, Scott Hauck
    Harnessing FPGAs for Computer Architecture Education. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:12-13 [Conf]
    
12. William V. Courtright II, Garth A. Gibson, Mark Holland, Jim Zelenka
    RAIDframe: Rapid Prototyping for Disk Arrays. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1996, pp:268-269 [Conf]