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Anant Agarwal: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Anant Agarwal, Richard Simoni, John L. Hennessy, Mark Horowitz
    An Evaluation of Directory Schemes for Cache Coherence. [Citation Graph (1, 0)][DBLP]
    ISCA, 1988, pp:280-289 [Conf]
  2. Anant Agarwal, John L. Hennessy, Mark Horowitz
    Cache Performance of Operating System and Multiprogramming Workloads. [Citation Graph (1, 0)][DBLP]
    ACM Trans. Comput. Syst., 1988, v:6, n:4, pp:393-431 [Journal]
  3. Anant Agarwal, Mark Horowitz, John L. Hennessy
    An Analytical Cache Model. [Citation Graph (1, 0)][DBLP]
    ACM Trans. Comput. Syst., 1989, v:7, n:2, pp:184-215 [Journal]
  4. David Chaiken, John Kubiatowicz, Anant Agarwal
    LimitLESS Directories: A Scalable Cache Coherence Scheme. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1991, pp:224-234 [Conf]
  5. John Kubiatowicz, David Chaiken, Anant Agarwal
    Closing the Window of Vulnerability in Multiphase Memory Transactions. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1992, pp:274-284 [Conf]
  6. Beng-Hong Lim, Anant Agarwal
    Reactive Synchronization Algorithms for Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1994, pp:25-35 [Conf]
  7. Susan S. Owicki, Anant Agarwal
    Evaluating the Performance of Software Cache Coherence. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1989, pp:230-242 [Conf]
  8. Jason E. Miller, Anant Agarwal
    Software-based instruction caching for embedded processors. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:293-302 [Conf]
  9. David Wentzlaff, Anant Agarwal
    Constructing Virtual Architectures on a Tiled Processor. [Citation Graph (0, 0)][DBLP]
    CGO, 2006, pp:173-184 [Conf]
  10. Anant Agarwal, David A. Kranz, Rajeev Barua, Venkat Natarajan
    Optimal Tiling for Minimizing Communication in Distributed Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    Compiler Optimizations for Scalable Parallel Systems Languages, 2001, pp:285-338 [Conf]
  11. Jonathan Babb, Matthew Frank, Victor Lee, Elliot Waingold, Rajeev Barua, Michael Taylor, Jang Kim, Devabhaktuni Srikrishna, Anant Agarwal
    The RAW benchmark suite: computation structures for general purpose computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:134-144 [Conf]
  12. Csaba Andras Moritz, Donald Yeung, Anant Agarwal
    Exploring Optimal Cost-Performance Designs for Raw Microprocessors. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:12-27 [Conf]
  13. David Wentzlaff, Anant Agarwal
    A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level Computation. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:289-290 [Conf]
  14. Charles Selvidge, Anant Agarwal, Matthew Dahl, Jonathan Babb
    TIERS: Topology Independent Pipelined Routing and Scheduling for VirtualWire Compilation. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:25-31 [Conf]
  15. Frederic T. Chong, Rajeev Barua, Fredrik Dahlgren, John Kubiatowicz, Anant Agarwal
    The Sensitivity of Communication Mechanisms to Bandwidth and Latency. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:37-46 [Conf]
  16. Kenneth Mackenzie, John Kubiatowicz, Matthew Frank, Walter Lee, Victor Lee, Anant Agarwal, M. Frans Kaashoek
    Exploiting Two-Case Delivery for Fast Protected Messaging. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:231-242 [Conf]
  17. Michael Bedford Taylor, Walter Lee, Saman P. Amarasinghe, Anant Agarwal
    Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:341-353 [Conf]
  18. Anant Agarwal, David A. Kranz, Venkat Natarajan
    Automatic Partitioning of Parallel Loops for Cache-Coherent Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:2-11 [Conf]
  19. G. N. Srinivasa Prasanna, Anant Agarwal
    Compile-time Techniques for Processor Allocation in Macro Dataflow Graphs for Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1992, pp:279-283 [Conf]
  20. John Kubiatowicz, Anant Agarwal
    Anatomy of a Message in the Alewife Multiprocessor. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1993, pp:195-206 [Conf]
  21. Anant Agarwal
    Retrospective: The MIT Alewife Machine: Architecture and Performance. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:103-110 [Conf]
  22. Anant Agarwal, Ricardo Bianchini, David Chaiken, Kirk L. Johnson, David A. Kranz
    The MIT Alewife Machine: Architecture and Performance. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:509-520 [Conf]
  23. Anant Agarwal, Ricardo Bianchini, David Chaiken, Kirk L. Johnson, David A. Kranz, John Kubiatowicz, Beng-Hong Lim, Kenneth Mackenzie, Donald Yeung
    The MIT Alewife Machine: Architecture and Performance. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:2-13 [Conf]
  24. Anant Agarwal, Mathews Cherian
    Adaptive Backoff Synchronization Techniques. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:396-406 [Conf]
  25. Anant Agarwal, Beng-Hong Lim, David A. Kranz, John Kubiatowicz
    APRIL: A Processor Architecture for Multiprocessing. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:104-114 [Conf]
  26. Anant Agarwal, Steven D. Pudar
    Column-Associative Caches: A Technique for Reducing the Miss Rate of Direct-Mapped Caches. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:179-190 [Conf]
  27. Anant Agarwal, Richard L. Sites, Mark Horowitz
    ATUM: A New Technique for Capturing Address Traces Using Microcode. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:119-127 [Conf]
  28. Rajeev Barua, Walter Lee, Saman P. Amarasinghe, Anant Agarwal
    Maps: A Compiler-Managed Memory System for Raw Machines. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:4-15 [Conf]
  29. Anant Agarwal, Richard Simoni, John L. Hennessy, Mark Horowitz
    An Evaluation of Directory Schemes for Cache Coherence. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:353-362 [Conf]
  30. David Chaiken, Anant Agarwal
    Software-Extended Coherent Shared Memory: Performance and Cost. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:314-324 [Conf]
  31. Richard L. Sites, Anant Agarwal
    Multiprocessor Cache Analysis Using ATUM. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:186-195 [Conf]
  32. Michael Bedford Taylor, Walter Lee, Jason E. Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Sungtae Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matthew Frank, Saman P. Amarasinghe, Anant Agarwal
    Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:2-13 [Conf]
  33. Donald Yeung, John Kubiatowicz, Anant Agarwal
    MGS: A Multigrain Shared Memory System. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:44-55 [Conf]
  34. Rajeev Barua, David A. Kranz, Anant Agarwal
    Communication-Minimal Partitioning of Parallel Loops and Data Arrays for Cache-Coherent Distributed-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    LCPC, 1996, pp:350-368 [Conf]
  35. Anant Agarwal, John V. Guttag, Christoforos N. Hadjicostis, Marios C. Papaefthymiou
    Memory Assignment for Multiprocessor Caches through Grey Coloring. [Citation Graph (0, 0)][DBLP]
    PARLE, 1994, pp:351-362 [Conf]
  36. Andrew Ayers, Richard Schooler, Chris Metcalf, Anant Agarwal, Junghwan Rhee, Emmett Witchel
    TraceBack: first fault diagnosis by reconstruction of distributed control flow. [Citation Graph (0, 0)][DBLP]
    PLDI, 2005, pp:201-212 [Conf]
  37. Matthew Frank, Anant Agarwal, Mary K. Vernon
    LoPC: Modeling Contention in Parallel Algorithms. [Citation Graph (0, 0)][DBLP]
    PPOPP, 1997, pp:276-287 [Conf]
  38. David A. Kranz, Kirk L. Johnson, Anant Agarwal, John Kubiatowicz, Beng-Hong Lim
    Integrating Message-Passing and Shared-Memory: Early Experience. [Citation Graph (0, 0)][DBLP]
    PPOPP, 1993, pp:54-63 [Conf]
  39. Donald Yeung, Anant Agarwal
    Experience with Fine-Grain Synchronization in MIMD Machines for Preconditioned Conjugate Gradient. [Citation Graph (0, 0)][DBLP]
    PPOPP, 1993, pp:187-197 [Conf]
  40. Anant Agarwal, Jonathan Babb, David Chaiken, Godfrey D'Souza, Kirk L. Johnson, David A. Kranz, John Kubiatowicz, Beng-Hong Lim, Gino Maa, Ken Mackenzie, Daniel Nussbaum, Mike Parkin, Donald Yeung
    Sparcle: A Multithreaded VLSI Processor for Parallel Computing. [Citation Graph (0, 0)][DBLP]
    Parallel Symbolic Computing, 1992, pp:359-361 [Conf]
  41. Anant Agarwal, Anoop Gupta
    Memory-Reference Characteristics of Multiprocessor Applications under MACH. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1988, pp:215-225 [Conf]
  42. Anant Agarwal, Minor Huffman
    Blocking: Exploiting Spatial Locality for Trace Compaction. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1990, pp:48-57 [Conf]
  43. Daniel Nussbaum, Ingmar Vuong-Adlerberg, Anant Agarwal
    Modeling a Circuit Switched Multiprocessor Interconnect. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1990, pp:267-269 [Conf]
  44. Jory Tsai, Anant Agarwal
    Analyzing Multiprocessor Cache Behavior Through Data Reference Modeling. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1993, pp:236-247 [Conf]
  45. David A. Kranz, Beng-Hong Lim, Kirk L. Johnson, John Kubiatowicz, Anant Agarwal
    Integrating Message-Passing and Shared-Memory: Early Experience. [Citation Graph (0, 0)][DBLP]
    SIGPLAN Workshop, 1992, pp:84- [Conf]
  46. Umar Saif, James W. Anderson, Anthony Degangi, Anant Agarwal
    Gigabit routing on a software-exposed tiled-microprocessor. [Citation Graph (0, 0)][DBLP]
    ANCS, 2005, pp:51-60 [Conf]
  47. Daniel Nussbaum, Anant Agarwal
    Scalability of Parallel Machines. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 1991, v:34, n:3, pp:57-61 [Journal]
  48. David Chaiken, Craig Fields, Kiyoshi Kurihara, Anant Agarwal
    Directory-Based cache Coherence in Large-Scale Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1990, v:23, n:6, pp:49-58 [Journal]
  49. Frederic T. Chong, Beng-Hong Lim, Ricardo Bianchini, John Kubiatowicz, Anant Agarwal
    Application Performance on the MIT Alewife Machine. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1996, v:29, n:12, pp:57-64 [Journal]
  50. Elliot Waingold, Michael Taylor, Devabhaktuni Srikrishna, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew Frank, Peter Finch, Rajeev Barua, Jonathan Babb, Saman P. Amarasinghe, Anant Agarwal
    Baring It All to Software: Raw Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:9, pp:86-93 [Journal]
  51. Michael Bedford Taylor, Jason Sungtae Kim, Jason E. Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jae-Wook Lee, Walter Lee, Albert Ma, Arvind Saraf, Mark Seneski, Nathan Shnidman, Volker Strumpen, Matthew Frank, Saman P. Amarasinghe, Anant Agarwal
    The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2002, v:22, n:2, pp:25-35 [Journal]
  52. Frederic T. Chong, Anant Agarwal
    Shared Memory Versus Message Passing for Iterative Solution of Sparse Irregular Problems. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1999, v:9, n:1, pp:159-170 [Journal]
  53. Rajeev Barua, Walter Lee, Saman P. Amarasinghe, Anant Agarwal
    Compiler Support for Scalable and Efficient Memory Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:11, pp:1234-1247 [Journal]
  54. Jonathan Babb, Russell Tessier, Matthew Dahl, Silvina Hanono, David M. Hoki, Anant Agarwal
    Logic emulation with virtual wires. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:6, pp:609-626 [Journal]
  55. Beng-Hong Lim, Anant Agarwal
    Waiting Algorithms for Synchronization in Large-Scale Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 1993, v:11, n:3, pp:253-294 [Journal]
  56. Donald Yeung, John Kubiatowicz, Anant Agarwal
    Multigrain shared memory. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 2000, v:18, n:2, pp:154-196 [Journal]
  57. Anant Agarwal
    Limits on Interconnection Network Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1991, v:2, n:4, pp:398-412 [Journal]
  58. Anant Agarwal
    Performance Tradeoffs in Multithreaded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1992, v:3, n:5, pp:525-539 [Journal]
  59. Anant Agarwal, David A. Kranz, Venkat Natarajan
    Automatic Partitioning of Parallel Loops and Data Arrays for Distributed Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1995, v:6, n:9, pp:943-962 [Journal]
  60. Csaba Andras Moritz, Donald Yeung, Anant Agarwal
    SimpleFit: A Framework for Analyzing Design Trade-Offs in Raw Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2001, v:12, n:7, pp:730-742 [Journal]
  61. G. N. Srinivasa Prasanna, Anant Agarwal, Bruce R. Musicus
    Hierarchical Compilation of Macro Dataflow Graphs for Multiprocessors with Local Memory. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1994, v:5, n:7, pp:720-736 [Journal]
  62. Michael Bedford Taylor, Walter Lee, Saman P. Amarasinghe, Anant Agarwal
    Scalar Operand Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:2, pp:145-162 [Journal]
  63. Anant Agarwal, Markus Levy
    The KILL Rule for Multicore. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:750-753 [Conf]
  64. David Wentzlaff, Patrick Griffin, Henry Hoffmann, Liewei Bao, Bruce Edwards, Carl Ramey, Matthew Mattina, Chyi-Chang Miao, John F. Brown III, Anant Agarwal
    On-Chip Interconnection Architecture of the Tile Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:5, pp:15-31 [Journal]

  65. rMPI: Message Passing on Multicore Processors with On-Chip Interconnect. [Citation Graph (, )][DBLP]


  66. Remote Store Programming. [Citation Graph (, )][DBLP]


  67. Application heartbeats for software performance and health. [Citation Graph (, )][DBLP]


  68. Keynote 3 (Banquet Talk) Digital space. [Citation Graph (, )][DBLP]


  69. An operating system for multicore and clouds: mechanisms and implementation. [Citation Graph (, )][DBLP]


  70. Thousand-Core Chips [Roundtable]. [Citation Graph (, )][DBLP]


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