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Bruce L. Jacob :
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Justin Teller , Charles B. Silio Jr. , Bruce Jacobs Performance characteristics of MAUI: an intelligent memory system architecture. [Citation Graph (0, 0)][DBLP ] Memory System Performance, 2005, pp:44-53 [Conf ] Hongxia Wang , Samuel Rodríguez , Cagdas Dirik , Amol Gole , Vincent Chan , Bruce Jacob TERPS: the embedded reliable processing system. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2005, pp:1-2 [Conf ] Bruce L. Jacob , Trevor N. Mudge A Look at Several Memory Management Units, TLB-Refill Mechanisms, and Page Table Organizations. [Citation Graph (0, 0)][DBLP ] ASPLOS, 1998, pp:295-306 [Conf ] Kathleen Baynes , Chris Collins , Eric Fiterman , Brinda Ganesh , Paul Kohout , Christine Smit , Tiebing Zhang , Bruce L. Jacob The performance and energy consumption of three embedded real-time operating systems. [Citation Graph (0, 0)][DBLP ] CASES, 2001, pp:203-210 [Conf ] Sadagopan Srinivasan , Vinodh Cuppu , Bruce L. Jacob Transparent data-memory organizations for digital signal processors. [Citation Graph (0, 0)][DBLP ] CASES, 2001, pp:44-48 [Conf ] Ankush Varma , Brinda Ganesh , Mainak Sen , Suchismita Roy Choudhury , Lakshmi Srinivasan , Bruce L. Jacob A control-theoretic approach to dynamic voltage scheduling. [Citation Graph (0, 0)][DBLP ] CASES, 2003, pp:255-266 [Conf ] Ankush Varma , Muhammad Yaqub Afridi , Akin Akturk , Paul Klein , Allen R. Hefner , Bruce L. Jacob Modeling heterogeneous SoCs with SystemC: a digital/MEMS case study. [Citation Graph (0, 0)][DBLP ] CASES, 2006, pp:54-64 [Conf ] Paul Kohout , Brinda Ganesh , Bruce L. Jacob Hardware support for real-time operating systems. [Citation Graph (0, 0)][DBLP ] CODES+ISSS, 2003, pp:45-51 [Conf ] Aamer Jaleel , Bruce L. Jacob Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers. [Citation Graph (0, 0)][DBLP ] HiPC, 2001, pp:282-293 [Conf ] Aamer Jaleel , Bruce L. Jacob Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions. [Citation Graph (0, 0)][DBLP ] HPCA, 2005, pp:191-200 [Conf ] Bruce L. Jacob , Trevor N. Mudge Software-Managed Address Translation. [Citation Graph (0, 0)][DBLP ] HPCA, 1997, pp:156-167 [Conf ] David R. Kaeli , Bruce Jacobs Fifth Annual Workshop on Computer Education. [Citation Graph (0, 0)][DBLP ] HPCA, 1999, pp:320- [Conf ] Aamer Jaleel , Bruce L. Jacob In-Line Interrupt Handling for Software-Managed TLBs. [Citation Graph (0, 0)][DBLP ] ICCD, 2001, pp:62-67 [Conf ] Vinodh Cuppu , Bruce L. Jacob Concurrency, latency, or system overhead: which has the largest impact on uniprocessor DRAM-system performance?. [Citation Graph (0, 0)][DBLP ] ISCA, 2001, pp:62-71 [Conf ] Vinodh Cuppu , Bruce L. Jacob , Brian Davis , Trevor N. Mudge A Performance Comparison of Contemporary DRAM Architectures. [Citation Graph (0, 0)][DBLP ] ISCA, 1999, pp:222-233 [Conf ] Bharath Iyer , Sadagopan Srinivasan , Bruce L. Jacob Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs. [Citation Graph (0, 0)][DBLP ] ISCA, 2004, pp:364-375 [Conf ] Brian Davis , Bruce L. Jacob , Trevor N. Mudge The New DRAM Interfaces: SDRAM, RDRAM and Variants. [Citation Graph (0, 0)][DBLP ] ISHPC, 2000, pp:26-31 [Conf ] Samuel Rodríguez , Bruce Jacob Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm). [Citation Graph (0, 0)][DBLP ] ISLPED, 2006, pp:25-30 [Conf ] Bruce L. Jacob , Trevor N. Mudge The trading function in action. [Citation Graph (0, 0)][DBLP ] ACM SIGOPS European Workshop, 1996, pp:241-247 [Conf ] Bruce L. Jacob , Trevor N. Mudge Virtual Memory: Issues of Implementation. [Citation Graph (0, 0)][DBLP ] IEEE Computer, 1998, v:31, n:6, pp:33-43 [Journal ] Bruce L. Jacob A Case for Studying DRAM Issues at the System Level. [Citation Graph (0, 0)][DBLP ] IEEE Micro, 2003, v:23, n:4, pp:44-56 [Journal ] David Wang , Brinda Ganesh , Nuengwong Tuaycharoen , Kathleen Baynes , Aamer Jaleel , Bruce L. Jacob DRAMsim: a memory system simulator. [Citation Graph (0, 0)][DBLP ] SIGARCH Computer Architecture News, 2005, v:33, n:4, pp:100-107 [Journal ] Kathleen Baynes , Chris Collins , Eric Fiterman , Brinda Ganesh , Paul Kohout , Christine Smit , Tiebing Zhang , Bruce L. Jacob The Performance and Energy Consumption of Embedded Real-Time Operating Systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2003, v:52, n:11, pp:1454-1469 [Journal ] Vinodh Cuppu , Bruce L. Jacob , Brian Davis , Trevor N. Mudge High-Performance DRAMs in Workstation Environments. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2001, v:50, n:11, pp:1133-1153 [Journal ] Bruce L. Jacob , Peter M. Chen , Seth R. Silverman , Trevor N. Mudge An Analytical Model for Designing Memory Hierarchies. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:10, pp:1180-1194 [Journal ] Bruce L. Jacob , Peter M. Chen , Seth R. Silverman , Trevor N. Mudge A Comment on ``An Analytical Model for Designing Memory Hierarchies''. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1997, v:46, n:10, pp:1151- [Journal ] Bruce L. Jacob , Trevor N. Mudge Uniprocessor Virtual Memory without TLBs. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2001, v:50, n:5, pp:482-499 [Journal ] Aamer Jaleel , Bruce L. Jacob In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs). [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2006, v:55, n:5, pp:559-574 [Journal ] Bruce L. Jacob , Shuvra S. Bhattacharyya Introduction to the two special issues on memory. [Citation Graph (0, 0)][DBLP ] ACM Trans. Embedded Comput. Syst., 2002, v:1, n:1, pp:2-5 [Journal ] Bruce L. Jacob , Shuvra S. Bhattacharyya Introduction to the two special issues on memory. [Citation Graph (0, 0)][DBLP ] ACM Trans. Embedded Comput. Syst., 2003, v:2, n:1, pp:1-4 [Journal ] Ankush Varma , Bruce L. Jacob , Eric Debes , Igor Kozintsev , Paul Klein Accurate and fast system-level power modeling: An XScale-based case study. [Citation Graph (0, 0)][DBLP ] ACM Trans. Embedded Comput. Syst., 2007, v:6, n:4, pp:- [Journal ] Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling. [Citation Graph (, )][DBLP ] Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads. [Citation Graph (, )][DBLP ] The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization. [Citation Graph (, )][DBLP ] BioBench: A Benchmark Suite of Bioinformatics Applications. [Citation Graph (, )][DBLP ] Search in 0.004secs, Finished in 0.006secs