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Li-Shiuan Peh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Philo Juang, Hidekazu Oki, Yong Wang, Margaret Martonosi, Li-Shiuan Peh, Daniel Rubenstein
    Energy-efficient computing for wildlife tracking: design tradeoffs and early experiences with ZebraNet. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2002, pp:96-107 [Conf]
  2. Noel Eisley, Li-Shiuan Peh
    High-level power analysis for on-chip networks. [Citation Graph (0, 0)][DBLP]
    CASES, 2004, pp:104-115 [Conf]
  3. Vassos Soteriou, Noel Eisley, Li-Shiuan Peh
    Software-directed power-aware interconnection networks. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:274-285 [Conf]
  4. Noel Eisley, Vassos Soteriou, Li-Shiuan Peh
    High-level power analysis for multi-core chips. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:389-400 [Conf]
  5. Amit Kumar 0002, Li Shang, Li-Shiuan Peh, Niraj K. Jha
    HybDTM: a coordinated hardware-software approach for dynamic thermal management. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:548-553 [Conf]
  6. Jiong Luo, Li-Shiuan Peh, Niraj K. Jha
    Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11150-11151 [Conf]
  7. Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
    A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1238-1243 [Conf]
  8. Wei Qin, Subramanian Rajagopalan, Manish Vachharajani, Hangsheng Wang, Xinping Zhu, David I. August, Kurt Keutzer, Sharad Malik, Li-Shiuan Peh
    Design Tools for Application Specific Embedded Processors. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2002, pp:319-333 [Conf]
  9. Xuning Chen, Li-Shiuan Peh, Gu-Yeon Wei, Yue-Kai Huang, Paul R. Prucnal
    Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:120-131 [Conf]
  10. Li-Shiuan Peh, William J. Dally
    Flit-Reservation Flow Control. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:73-84 [Conf]
  11. Li-Shiuan Peh, William J. Dally
    A Delay Model and Speculative Architecture for Pipelined Routers. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:255-266 [Conf]
  12. Li Shang, Li-Shiuan Peh, Niraj K. Jha
    Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:91-102 [Conf]
  13. Vassos Soteriou, Li-Shiuan Peh
    Design-Space Exploration of Power-Aware On/Off Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:510-517 [Conf]
  14. Li Shang, Li-Shiuan Peh, Niraj K. Jha
    PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks. [Citation Graph (0, 0)][DBLP]
    ICS, 2003, pp:98-108 [Conf]
  15. David I. August, Sharad Malik, Li-Shiuan Peh, Vijay S. Pai
    Achieving Structural and Composable Modeling of Complex Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS Next Generation Software Program - NSFNGS - PI Workshop, 2004, pp:- [Conf]
  16. Xuning Chen, Li-Shiuan Peh
    Leakage power modeling and optimization in interconnection networks. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:90-95 [Conf]
  17. Philo Juang, Qiang Wu, Li-Shiuan Peh, Margaret Martonosi, Douglas W. Clark
    Coordinated, distributed, formal energy management of chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:127-130 [Conf]
  18. Vassos Soteriou, Hangsheng Wang, Li-Shiuan Peh
    A Statistical Traffic Model for On-Chip Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 2006, pp:104-116 [Conf]
  19. Yong Wang, Margaret Martonosi, Li-Shiuan Peh
    Situation-Aware Caching Strategies in Highly Varying Mobile Networks. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 2006, pp:265-274 [Conf]
  20. Li Shang, Li-Shiuan Peh, Amit Kumar 0002, Niraj K. Jha
    Thermal Modeling, Characterization and Management of On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:67-78 [Conf]
  21. Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
    Power-driven Design of Router Microarchitectures in On-chip Networks. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:105-116 [Conf]
  22. Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad Malik
    Orion: a power-performance simulator for interconnection networks. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:294-305 [Conf]
  23. Noel Eisley, Li-Shiuan Peh, Li Shang
    In-Network Cache Coherence. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:321-332 [Conf]
  24. Yong Wang, Margaret Martonosi, Li-Shiuan Peh
    A new scheme on link quality prediction and its applications to metric-based routing. [Citation Graph (0, 0)][DBLP]
    SenSys, 2005, pp:288-289 [Conf]
  25. Li Shang, Li-Shiuan Peh, Niraj K. Jha
    Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links. [Citation Graph (0, 0)][DBLP]
    Computer Architecture Letters, 2002, v:1, n:, pp:- [Journal]
  26. Li-Shiuan Peh, Christopher Ting Hian Ann
    A Divide-and-Conquer Strategy for Parsing [Citation Graph (0, 0)][DBLP]
    CoRR, 1996, v:0, n:, pp:- [Journal]
  27. David I. August, Sharad Malik, Li-Shiuan Peh, Vijay S. Pai, Manish Vachharajani, Paul Willmann
    Achieving Structural and Composable Modeling of Complex Systems. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2005, v:33, n:2-3, pp:81-101 [Journal]
  28. Li-Shiuan Peh, William J. Dally
    A Delay Model for Router Microarchitectures. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2001, v:21, n:1, pp:26-34 [Journal]
  29. Li Shang, Li-Shiuan Peh, Amit Kumar 0002, Niraj K. Jha
    Temperature-Aware On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:1, pp:130-139 [Journal]
  30. Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
    A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:1, pp:26-35 [Journal]
  31. Qiang Wu, Philo Juang, Margaret Martonosi, Li-Shiuan Peh, Douglas W. Clark
    Formal Control Techniques for Power-Performance Management. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:5, pp:52-62 [Journal]
  32. Julia Chen, Philo Juang, Kevin Ko, Gilberto Contreras, David Penry, Ram Rangan, Adam Stoler, Li-Shiuan Peh, Margaret Martonosi
    Hardware-modulated parallelism in chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:4, pp:54-63 [Journal]
  33. Yong Wang, Margaret Martonosi, Li-Shiuan Peh
    MARio: mobility-adaptive routing using route lifetime abstractions in mobile ad hoc networks. [Citation Graph (0, 0)][DBLP]
    Mobile Computing and Communications Review, 2004, v:8, n:4, pp:77-81 [Journal]
  34. Li Shang, Li-Shiuan Peh, Niraj K. Jha
    PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:92-110 [Journal]
  35. Li-Shiuan Peh, Timothy Mark Pinkston
    Guest Editorial: Special Section on On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:2, pp:97-98 [Journal]
  36. Vassos Soteriou, Li-Shiuan Peh
    Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:3, pp:393-408 [Journal]
  37. Amit Kumar 0002, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha
    Express virtual channels: towards the ideal interconnection fabric. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:150-161 [Conf]
  38. John D. Owens, William J. Dally, Ron Ho, D. N. Jayasimha, Stephen W. Keckler, Li-Shiuan Peh
    Research Challenges for On-Chip Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:5, pp:96-108 [Journal]
  39. Partha Kundu, Li-Shiuan Peh
    Guest Editors' Introduction: On-Chip Interconnects for Multicores. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:5, pp:3-5 [Journal]
  40. Vassos Soteriou, Noel Eisley, Li-Shiuan Peh
    Software-directed power-aware interconnection networks. [Citation Graph (0, 0)][DBLP]
    TACO, 2007, v:4, n:1, pp:- [Journal]
  41. Jiong Luo, Niraj K. Jha, Li-Shiuan Peh
    Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:4, pp:427-437 [Journal]
  42. Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li-Shiuan Peh
    Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:855-868 [Journal]

  43. Leveraging on-chip networks for data cache migration in chip multiprocessors. [Citation Graph (, )][DBLP]


  44. Extending open core protocol to support system-level cache coherence. [Citation Graph (, )][DBLP]


  45. ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration. [Citation Graph (, )][DBLP]


  46. A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers. [Citation Graph (, )][DBLP]


  47. NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication. [Citation Graph (, )][DBLP]


  48. In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects. [Citation Graph (, )][DBLP]


  49. Polaris: A System-Level Roadmap for On-Chip Interconnection Networks. [Citation Graph (, )][DBLP]


  50. A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS. [Citation Graph (, )][DBLP]


  51. A system-level perspective for efficient NoC design. [Citation Graph (, )][DBLP]


  52. Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support. [Citation Graph (, )][DBLP]


  53. Design of low-power short-distance opto-electronic transceiver front-ends with scalable supply voltages and frequencies. [Citation Graph (, )][DBLP]


  54. GARNET: A detailed on-chip network model inside a full-system simulator. [Citation Graph (, )][DBLP]


  55. Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence. [Citation Graph (, )][DBLP]


  56. Token flow control. [Citation Graph (, )][DBLP]


  57. In-network coherence filtering: snoopy coherence without broadcasts. [Citation Graph (, )][DBLP]


  58. Circuit-Switched Coherence. [Citation Graph (, )][DBLP]


  59. Impact of Process and Temperature Variations on Network-on-Chip Design Exploration. [Citation Graph (, )][DBLP]


  60. Design of a High-Throughput Distributed Shared-Buffer NoC Router. [Citation Graph (, )][DBLP]


  61. Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs. [Citation Graph (, )][DBLP]


  62. In-network cache coherence. [Citation Graph (, )][DBLP]


  63. Circuit-Switched Coherence. [Citation Graph (, )][DBLP]


  64. Thousand-Core Chips [Roundtable]. [Citation Graph (, )][DBLP]


  65. Guest Editors' Introduction: Tackling Key Problems in NoCs. [Citation Graph (, )][DBLP]


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