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Robert Cohn: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Robert Cohn, Thomas R. Gross, Monica S. Lam, P. S. Tseng
    Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1989, pp:2-14 [Conf]
  2. Vijay Janapa Reddi, Dan Connors, Robert Cohn, Michael D. Smith
    Persistent Code Caching: Exploiting Code Reuse Across Executions and Applications. [Citation Graph (0, 0)][DBLP]
    CGO, 2007, pp:74-88 [Conf]
  3. Marco Annaratone, Emmanuel A. Arnould, Robert Cohn, Thomas R. Gross, H. T. Kung, Monica S. Lam, Onat Menzilcioglu, Ken Sarocky, John Senko, Jon A. Webb
    Architecture of Warp. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1987, pp:264-267 [Conf]
  4. Bernd Bruegge, Chang-Hsin Chang, Robert Cohn, Thomas R. Gross, Monica S. Lam, Peter Lieu, Abu Noaman, David Yam
    Programming Warp. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1987, pp:268-271 [Conf]
  5. Shekhar Borkar, Robert Cohn, George W. Cox, Thomas R. Gross, H. T. Kung, Monica S. Lam, Margie Levine, Brian Moore, Wire Moore, Craig Peterson, Jim Susman, Jim Sutton, John Urbanski, Jon A. Webb
    Supporting Systolic and Memory Communciation in iWarp. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:70-81 [Conf]
  6. Robert Cohn
    Source Level Debugging of Automatically Parallelized Code. [Citation Graph (0, 0)][DBLP]
    Workshop on Parallel and Distributed Debugging, 1991, pp:132-143 [Conf]
  7. Shekhar Borkar, Robert Cohn, George W. Cox, Sha Gleason, Thomas R. Gross
    Warp: an integrated solution of high-speed parallel computing. [Citation Graph (0, 0)][DBLP]
    SC, 1988, pp:330-339 [Conf]
  8. Satish Narayanasamy, Cristiano Pereira, Harish Patil, Robert Cohn, Brad Calder
    Automatic logging of operating system effects to guide application-level architecture simulation. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS/Performance, 2006, pp:216-227 [Conf]
  9. Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn
    VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:424-435 [Conf]

  10. Scalable support for multithreaded applications on dynamic binary instrumentation systems. [Citation Graph (, )][DBLP]


  11. Analyzing Parallel Programs with Pin. [Citation Graph (, )][DBLP]


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