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Publications of Author

1. Changkyu Kim, Doug Burger, Stephen W. Keckler
   An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches. [Citation Graph (0, 0)][DBLP]
   ASPLOS, 2002, pp:211-222 [Conf]
   
2. Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang, Doug Burger, Stephen W. Keckler
   A NUCA substrate for flexible CMP cache sharing. [Citation Graph (0, 0)][DBLP]
   ICS, 2005, pp:31-40 [Conf]
   
3. Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore
   Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture. [Citation Graph (0, 0)][DBLP]
   ISCA, 2003, pp:422-433 [Conf]
   
4. Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger
   Distributed Microarchitectural Protocols in the TRIPS Prototype Processor. [Citation Graph (0, 0)][DBLP]
   MICRO, 2006, pp:480-491 [Conf]
   
5. Changkyu Kim, Doug Burger, Stephen W. Keckler
   Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches. [Citation Graph (0, 0)][DBLP]
   IEEE Micro, 2003, v:23, n:6, pp:99-107 [Journal]
   
6. Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore
   Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture. [Citation Graph (0, 0)][DBLP]
   IEEE Micro, 2003, v:23, n:6, pp:46-51 [Journal]
   
7. Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, Charles R. Moore
   TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP. [Citation Graph (0, 0)][DBLP]
   TACO, 2004, v:1, n:1, pp:62-93 [Journal]
   
8. Paul Gratz, Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger
   On-Chip Interconnection Networks of the TRIPS Chip. [Citation Graph (0, 0)][DBLP]
   IEEE Micro, 2007, v:27, n:5, pp:41-50 [Journal]
   
9. Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang, Doug Burger, Stephen W. Keckler
   A NUCA Substrate for Flexible CMP Cache Sharing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:8, pp:1028-1040 [Journal]
   
10. 
    Multitasking workload scheduling on flexible-core chip multiprocessors. [Citation Graph (, )][DBLP]
    
    
11. 
    Implementation and Evaluation of On-Chip Network Architectures. [Citation Graph (, )][DBLP]
    
    
12. 
    Efficient shared cache management through sharing-aware replacement and streaming-aware insertion policy. [Citation Graph (, )][DBLP]
    
    
13. 
    Atomic Vector Operations on Chip Multiprocessors. [Citation Graph (, )][DBLP]
    
    
14. 
    Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU. [Citation Graph (, )][DBLP]
    
    
15. 
    Composable Lightweight Processors. [Citation Graph (, )][DBLP]
    
    
16. 
    FAST: fast architecture sensitive tree search on modern CPUs and GPUs. [Citation Graph (, )][DBLP]
    
    
17. 
    Fast sort on CPUs and GPUs: a case for bandwidth oblivious SIMD sort. [Citation Graph (, )][DBLP]
    
    
18. 
    ClearPath: highly parallel collision avoidance for multi-agent simulation. [Citation Graph (, )][DBLP]
    
    
19. 
    Interactive Modeling, Simulation and Control of Large-Scale Crowds and Traffic. [Citation Graph (, )][DBLP]
    
    
20. 
    Second Life and the New Generation of Virtual Worlds. [Citation Graph (, )][DBLP]