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Publications of Author

1. Rajagopalan Desikan, Simha Sethumadhavan, Doug Burger, Stephen W. Keckler
   Scalable selective re-execution for EDGE architectures. [Citation Graph (0, 0)][DBLP]
   ASPLOS, 2004, pp:120-132 [Conf]
   
2. Karthikeyan Sankaralingam, Simha Sethumadhavan, James C. Browne
   Distributed Pagerank for P2P Systems. [Citation Graph (0, 0)][DBLP]
   HPDC, 2003, pp:58-69 [Conf]
   
3. Gregory S. Johnson, Simha Sethumadhavan
   Compiler Directed Parallelization of Loops in Scale for Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
   International Conference on Computational Science, 2003, pp:946-955 [Conf]
   
4. Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler
   Scalable Hardware Memory Disambiguation for High ILP Processors. [Citation Graph (0, 0)][DBLP]
   MICRO, 2003, pp:399-410 [Conf]
   
5. Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger
   Distributed Microarchitectural Protocols in the TRIPS Prototype Processor. [Citation Graph (0, 0)][DBLP]
   MICRO, 2006, pp:480-491 [Conf]
   
6. Karthikeyan Sankaralingam, Madhulika Yalamanchi, Simha Sethumadhavan, James C. Browne
   Pagerank Computation and Keyword Search on Distributed Systems and P2P Networks. [Citation Graph (0, 0)][DBLP]
   J. Grid Comput., 2003, v:1, n:3, pp:291-307 [Journal]
   
7. Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler
   Scalable Hardware Memory Disambiguation for High-ILP Processors. [Citation Graph (0, 0)][DBLP]
   IEEE Micro, 2004, v:24, n:6, pp:118-127 [Journal]
   
8. Simha Sethumadhavan, Franziska Roesner, Joel S. Emer, Doug Burger, Stephen W. Keckler
   Late-binding: enabling unordered load-store queues. [Citation Graph (0, 0)][DBLP]
   ISCA, 2007, pp:347-357 [Conf]
   
9. 
   Multitasking workload scheduling on flexible-core chip multiprocessors. [Citation Graph (, )][DBLP]
   
   
10. 
    Design and Implementation of the TRIPS Primary Memory System. [Citation Graph (, )][DBLP]
    
    
11. 
    Composable Lightweight Processors. [Citation Graph (, )][DBLP]
    
    
12. 
    Tamper Evident Microprocessors. [Citation Graph (, )][DBLP]