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Alvin R. Lebeck: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alvin R. Lebeck, David A. Wood
    Cache Profiling and the SPEC Benchmarks: A Case Study. [Citation Graph (1, 0)][DBLP]
    IEEE Computer, 1994, v:27, n:10, pp:15-26 [Journal]
  2. Ioannis Schoinas, Babak Falsafi, Alvin R. Lebeck, Steven K. Reinhardt, James R. Larus, David A. Wood
    Fine-grain Access Control for Distributed Shared Memory. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1994, pp:297-306 [Conf]
  3. Alvin R. Lebeck, Xiaobo Fan, Heng Zeng, Carla Schlatter Ellis
    Power Aware Page Allocation. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2000, pp:105-116 [Conf]
  4. Heng Zeng, Carla Schlatter Ellis, Alvin R. Lebeck, Amin Vahdat
    ECOSystem: managing energy as a first class operating system resource. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2002, pp:123-132 [Conf]
  5. Jaidev P. Patwardhan, Vijeta Johri, Chris Dwyer, Alvin R. Lebeck
    A defect tolerant self-organizing nanoscale SIMD architecture. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:241-251 [Conf]
  6. Constantin Pistol, Alvin R. Lebeck, Chris Dwyer
    Design automation for DNA self-assembled nanostructures. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:919-924 [Conf]
  7. Alvin R. Lebeck, David R. Raymond, Chia-Lin Yang, Mithuna Thottethodi
    Annotated Memory References: A Mechanism for Informed Cache Management. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:1251-1254 [Conf]
  8. Mithuna Thottethodi, Alvin R. Lebeck, Shubhendu S. Mukherjee
    Self-Tuned Congestion Control for Multiprocessor Networks. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:107-0 [Conf]
  9. Ken Yocum, Jeffrey S. Chase, Andrew J. Gallatin, Alvin R. Lebeck
    Cut-Through Delivery in Trapeze: An Exercise in Low-Latency Messaging. [Citation Graph (0, 0)][DBLP]
    HPDC, 1997, pp:243-0 [Conf]
  10. Siddhartha Chatterjee, Vibhor V. Jain, Alvin R. Lebeck, Shyam Mundhra, Mithuna Thottethodi
    Nonlinear array layouts for hierarchical memory systems. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:444-453 [Conf]
  11. Chia-Lin Yang, Alvin R. Lebeck
    Push vs. pull: data movement for linked data structures. [Citation Graph (0, 0)][DBLP]
    ICS, 2000, pp:176-186 [Conf]
  12. Mithuna Thottethodi, Alvin R. Lebeck, Shubhendu S. Mukherjee
    BLAM : A High-Performance Routing Algorithm for Virtual Cut-Through Networks. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:45- [Conf]
  13. Richard E. Kessler, Richard Jooss, Alvin R. Lebeck, Mark D. Hill
    Inexpensive Implementations of Set-Associativity. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:131-139 [Conf]
  14. Alvin R. Lebeck, Tong Li, Eric Rotenberg, Jinson Koppanalil, Jaidev P. Patwardhan
    A Large, Fast Instruction Window for Tolerating Cache Misses. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:59-70 [Conf]
  15. Alvin R. Lebeck, David A. Wood
    Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:48-59 [Conf]
  16. Srikanth T. Srinivasan, Roy Dz-Ching Ju, Alvin R. Lebeck, Chris Wilkerson
    Locality vs. criticality. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:132-143 [Conf]
  17. David A. Wood, Satish Chandra, Babak Falsafi, Mark D. Hill, James R. Larus, Alvin R. Lebeck, James C. Lewis, Shubhendu S. Mukherjee, Subbarao Palacharla, Steven K. Reinhardt
    Mechanisms for Cooperative Shared Memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:156-167 [Conf]
  18. Chia-Lin Yang, Alvin R. Lebeck
    A Programmable Memory Hierarchy for Prefetching Linked Data Structures. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2002, pp:160-174 [Conf]
  19. Xiaobo Fan, Carla Schlatter Ellis, Alvin R. Lebeck
    Memory controller policies for DRAM power management. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:129-134 [Conf]
  20. Jaidev P. Patwardhan, Alvin R. Lebeck, Daniel J. Sorin
    Communication breakdown: analyzing CPU usage in commercial Web workloads. [Citation Graph (0, 0)][DBLP]
    ISPASS, 2004, pp:12-19 [Conf]
  21. Srikanth T. Srinivasan, Alvin R. Lebeck
    Load Latency Tolerance in Dynamically Scheduled Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:148-159 [Conf]
  22. Chia-Lin Yang, Barton Sano, Alvin R. Lebeck
    Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:14-24 [Conf]
  23. Xiaobo Fan, Carla Schlatter Ellis, Alvin R. Lebeck
    Modeling of DRAM Power Control Policies Using Deterministic and Stochastic Petri Nets. [Citation Graph (0, 0)][DBLP]
    PACS, 2002, pp:130-140 [Conf]
  24. Xiaobo Fan, Carla Schlatter Ellis, Alvin R. Lebeck
    The Synergy Between Power-Aware Memory Systems and Processor Voltage Scaling. [Citation Graph (0, 0)][DBLP]
    PACS, 2003, pp:164-179 [Conf]
  25. Siddhartha Chatterjee, Erin Parker, Philip J. Hanlon, Alvin R. Lebeck
    Exact Analysis of the Cache Behavior of Nested Loops. [Citation Graph (0, 0)][DBLP]
    PLDI, 2001, pp:286-297 [Conf]
  26. Babak Falsafi, Alvin R. Lebeck, Steven K. Reinhardt, Ioannis Schoinas, Mark D. Hill, James R. Larus, Anne Rogers, David A. Wood
    Application-specific protocols for user-level shared memory. [Citation Graph (0, 0)][DBLP]
    SC, 1994, pp:380-389 [Conf]
  27. Alvin R. Lebeck
    Cache conscious programming in undergraduate computer science. [Citation Graph (0, 0)][DBLP]
    SIGCSE, 1999, pp:247-251 [Conf]
  28. Alvin R. Lebeck, David A. Wood
    Active Memory: A New Abstraction for Memory-System Simulation. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1995, pp:220-231 [Conf]
  29. Steven K. Reinhardt, Mark D. Hill, James R. Larus, Alvin R. Lebeck, James C. Lewis, David A. Wood
    The Wisconsin Wind Tunnel: Virtual Prototyping of Parallel Computers. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1993, pp:48-60 [Conf]
  30. Amin Vahdat, Alvin R. Lebeck, Carla Schlatter Ellis
    Every joule is precious: the case for revisiting operating system design for energy efficiency. [Citation Graph (0, 0)][DBLP]
    ACM SIGOPS European Workshop, 2000, pp:31-36 [Conf]
  31. Siddhartha Chatterjee, Alvin R. Lebeck, Praveen K. Patnala, Mithuna Thottethodi
    Recursive Array Layouts and Fast Parallel Matrix Multiplication. [Citation Graph (0, 0)][DBLP]
    SPAA, 1999, pp:222-231 [Conf]
  32. Tong Li, Alvin R. Lebeck, Daniel J. Sorin
    Quantifying instruction criticality for shared memory multiprocessors. [Citation Graph (0, 0)][DBLP]
    SPAA, 2003, pp:128-137 [Conf]
  33. Heng Zeng, Carla Schlatter Ellis, Alvin R. Lebeck, Amin Vahdat
    Currentcy: A Unifying Abstraction for Expressing Energy Management Policies. [Citation Graph (0, 0)][DBLP]
    USENIX Annual Technical Conference, General Track, 2003, pp:43-56 [Conf]
  34. Tong Li, Carla Schlatter Ellis, Alvin R. Lebeck, Daniel J. Sorin
    Pulse: A Dynamic Deadlock Detection Mechanism Using Speculative Execution. [Citation Graph (0, 0)][DBLP]
    USENIX Annual Technical Conference, General Track, 2005, pp:31-44 [Conf]
  35. Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin
    Self-Assembled Architectures and the Temporal Aspects of Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2005, v:38, n:1, pp:56-64 [Journal]
  36. Philip J. Hanlon, Dean Chung, Siddhartha Chatterjee, Daniela Genius, Alvin R. Lebeck, Erin Parker
    The Combinatorics of Cache Misses during Matrix Multiplication. [Citation Graph (0, 0)][DBLP]
    J. Comput. Syst. Sci., 2001, v:63, n:1, pp:80-126 [Journal]
  37. Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin
    NANA: A nano-scale active network architecture. [Citation Graph (0, 0)][DBLP]
    JETC, 2006, v:2, n:1, pp:1-30 [Journal]
  38. Srikanth T. Srinivasan, Alvin R. Lebeck
    Load Latency Tolerance in Dynamically Scheduled Processors. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 1999, v:1, n:, pp:- [Journal]
  39. Chia-Lin Yang, Alvin R. Lebeck, Hung-Wei Tseng, Chien-Hao Lee
    Tolerating memory latency through push prefetching for pointer-intensive applications. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:4, pp:445-475 [Journal]
  40. Chia-Lin Yang, Barton Sano, Alvin R. Lebeck
    Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:9, pp:934-946 [Journal]
  41. Alvin R. Lebeck, David A. Wood
    Active Memory: A New Abstraction for Memory System Simulation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Model. Comput. Simul., 1997, v:7, n:1, pp:42-77 [Journal]
  42. Siddhartha Chatterjee, Alvin R. Lebeck, Praveen K. Patnala, Mithuna Thottethodi
    Recursive Array Layouts and Fast Matrix Multiplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2002, v:13, n:11, pp:1105-1123 [Journal]
  43. Alvin R. Lebeck, Gurindar S. Sohi
    Request Combining in Multiprocessors with Arbitrary Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1994, v:5, n:11, pp:1140-1155 [Journal]
  44. Tong Li, Alvin R. Lebeck, Daniel J. Sorin
    Spin Detection Hardware for Improved Management of Multithreaded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2006, v:17, n:6, pp:508-521 [Journal]
  45. Mithuna Thottethodi, Alvin R. Lebeck, Shubhendu S. Mukherjee
    Exploiting Global Knowledge to Achieve Self-Tuned Congestion Control for k-Ary n-Cube Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2004, v:15, n:3, pp:257-272 [Journal]
  46. Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck
    A self-organizing defect tolerant SIMD architecture. [Citation Graph (0, 0)][DBLP]
    JETC, 2007, v:3, n:2, pp:- [Journal]

  47. Architectural implications of nanoscale integrated sensing and computing. [Citation Graph (, )][DBLP]


  48. Specifying and dynamically verifying address translation-aware memory consistency. [Citation Graph (, )][DBLP]


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