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Publications of Author

1. André Seznec, Stéphan Jourdan, Pascal Sainrat, Pierre Michaud
   Multiple-Block Ahead Branch Predictors. [Citation Graph (0, 0)][DBLP]
   ASPLOS, 1996, pp:116-127 [Conf]
   
2. Christine Rochange, Pascal Sainrat
   A time-predictable execution mode for superscalar pipelines with instruction prescheduling. [Citation Graph (0, 0)][DBLP]
   Conf. Computing Frontiers, 2005, pp:307-314 [Conf]
   
3. Pascal Sainrat, Mateo Valero
   Instruction-Level Parallelism and Uniprocessor Architecture - Introduction. [Citation Graph (0, 0)][DBLP]
   Euro-Par, 1999, pp:1241-1242 [Conf]
   
4. Stéphan Jourdan, Pascal Sainrat, Daniel Litaize
   Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor. [Citation Graph (0, 0)][DBLP]
   ISCA, 1995, pp:117-125 [Conf]
   
5. Daniel Litaize, Abdelaziz Mzoughi, Christine Rochange, Pascal Sainrat
   Towards a Shared-Memory Massively Parallel Multiprocessor. [Citation Graph (0, 0)][DBLP]
   ISCA, 1992, pp:70-79 [Conf]
   
6. Stéphan Jourdan, Pascal Sainrat, Daniel Litaize
   An investigation of the performance of various instruction-issue buffer topologies. [Citation Graph (0, 0)][DBLP]
   MICRO, 1995, pp:279-284 [Conf]
   
7. Daniel Litaize, Fatimazhra Elkhlifi, Omar Hammami, Mustapha Lalam, Abdelaziz Mzoughi, Pascal Sainrat, Jean-Claude Salinier
   Serial Multiport Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
   PARLE (1), 1989, pp:34-51 [Conf]
   
8. Christine Rochange, Pascal Sainrat, Daniel Litaize
   Performance of M3S for the SOR algorithm. [Citation Graph (0, 0)][DBLP]
   PARLE, 1993, pp:676-679 [Conf]
   
9. Jonathan Barre, Cédric Landet, Christine Rochange, Pascal Sainrat
   Modeling Instruction-Level Parallelism for WCET Evaluation. [Citation Graph (0, 0)][DBLP]
   RTCSA, 2006, pp:61-67 [Conf]
   
10. Claire Burguière, Christine Rochange, Pascal Sainrat
    A Case for Static Branch Prediction in Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2005, pp:33-38 [Conf]
    
11. Pascal Sainrat, Abdelaziz Mzoughi, Christine Rochange, Daniel Litaize
    The Design of the M3S: A Multiported Shared-Memory Multiprocessor. [Citation Graph (0, 0)][DBLP]
    SC, 1992, pp:326-335 [Conf]
    
12. Christine Rochange, Pascal Sainrat
    Towards Designing WCET-Predictable Processors. [Citation Graph (0, 0)][DBLP]
    WCET, 2003, pp:87-90 [Conf]
    
13. Antoine Colin, Isabelle Puaut, Christine Rochange, Pascal Sainrat
    Calcul de majorants de pire temps d'exécution : état de l'art. [Citation Graph (0, 0)][DBLP]
    Technique et Science Informatiques, 2003, v:22, n:5, pp:651-677 [Journal]
    
14. H. Cassé, L. Féraud, Christine Rochange, Pascal Sainrat
    Une approche pour réduire la complexité du flot de contrôle dans les programmes C. [Citation Graph (0, 0)][DBLP]
    Technique et Science Informatiques, 2002, v:21, n:7, pp:1009-1032 [Journal]
    
15. Thierry Haquin, Philippe Reynes, Christine Rochange, Pascal Sainrat
    Optimisations du chargement des instructions. [Citation Graph (0, 0)][DBLP]
    Technique et Science Informatiques, 2003, v:22, n:6, pp:689-711 [Journal]
    
16. 
    A Predictable Simultaneous Multithreading Scheme for Hard Real-Time. [Citation Graph (, )][DBLP]
    
    
17. 
    Experimentation of WCET computation on both ends of automotive processor range. [Citation Graph (, )][DBLP]
    
    
18. 
    Static Loop Bound Analysis of C Programs Based on Flow Analysis and Abstract Interpretation. [Citation Graph (, )][DBLP]
    
    
19. 
    An improved approach for set-associative instruction cache partial analysis. [Citation Graph (, )][DBLP]
    
    
20. 
    An architecture for the simultaneous execution of hard real-time threads. [Citation Graph (, )][DBLP]
    
    
21. 
    WCET 2008 - Report from the Tool Challenge 2008 -- 8th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis. [Citation Graph (, )][DBLP]
    
    
22. 
    Combining Symbolic Execution and Path Enumeration in Worst-Case Execution Time Analysis. [Citation Graph (, )][DBLP]
    
    
23. 
    PapaBench: a Free Real-Time Benchmark. [Citation Graph (, )][DBLP]
    
    
24. 
    Inter-task WCET computation for a-way instruction caches. [Citation Graph (, )][DBLP]
    
    
25. 
    Improving the Worst-Case Execution Time Accuracy by Inter-Task Instruction Cache Analysis. [Citation Graph (, )][DBLP]