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Jonathan Babb: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Walter Lee, Rajeev Barua, Matthew Frank, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, Saman P. Amarasinghe
Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine. [Citation Graph (0, 0)][DBLP]
ASPLOS, 1998, pp:46-57 [Conf] - Jonathan Babb, Matthew Frank, Victor Lee, Elliot Waingold, Rajeev Barua, Michael Taylor, Jang Kim, Devabhaktuni Srikrishna, Anant Agarwal
The RAW benchmark suite: computation structures for general purpose computing. [Citation Graph (0, 0)][DBLP]
FCCM, 1997, pp:134-144 [Conf] - Jonathan Babb, Martin C. Rinard, Csaba Andras Moritz, Walter Lee, Matthew Frank, Rajeev Barua, Saman P. Amarasinghe
Parallelizing Applications into Silicon. [Citation Graph (0, 0)][DBLP]
FCCM, 1999, pp:70-0 [Conf] - Charles Selvidge, Anant Agarwal, Matthew Dahl, Jonathan Babb
TIERS: Topology Independent Pipelined Routing and Scheduling for VirtualWire Compilation. [Citation Graph (0, 0)][DBLP]
FPGA, 1995, pp:25-31 [Conf] - Mark Stephenson, Jonathan Babb, Saman P. Amarasinghe
Bitwidth analysis with application to silicon compilation. [Citation Graph (0, 0)][DBLP]
PLDI, 2000, pp:108-120 [Conf] - Anant Agarwal, Jonathan Babb, David Chaiken, Godfrey D'Souza, Kirk L. Johnson, David A. Kranz, John Kubiatowicz, Beng-Hong Lim, Gino Maa, Ken Mackenzie, Daniel Nussbaum, Mike Parkin, Donald Yeung
Sparcle: A Multithreaded VLSI Processor for Parallel Computing. [Citation Graph (0, 0)][DBLP]
Parallel Symbolic Computing, 1992, pp:359-361 [Conf] - Elliot Waingold, Michael Taylor, Devabhaktuni Srikrishna, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew Frank, Peter Finch, Rajeev Barua, Jonathan Babb, Saman P. Amarasinghe, Anant Agarwal
Baring It All to Software: Raw Machines. [Citation Graph (0, 0)][DBLP]
IEEE Computer, 1997, v:30, n:9, pp:86-93 [Journal] - Jonathan Babb, Russell Tessier, Matthew Dahl, Silvina Hanono, David M. Hoki, Anant Agarwal
Logic emulation with virtual wires. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:6, pp:609-626 [Journal]
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