The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

James C. Hoe: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas Nowatzyk
    Fingerprinting: bounding soft-error detection latency and bandwidth. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2004, pp:224-234 [Conf]
  2. Grace Nordin, Peter A. Milder, James C. Hoe, Markus Püschel
    Automatic generation of customized discrete fourier transform IPs. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:471-474 [Conf]
  3. Peter Tummeltshammer, James C. Hoe, Markus Püschel
    Multiple constant multiplication by time-multiplexed mapping of addition chains. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:826-829 [Conf]
  4. Derek Chiou, Boon Seong Ang, Robert Greiner, Arvind, James C. Hoe, Michael J. Beckerle, James E. Hicks, G. Andrew Boughton
    START-NG: Delivering Seamless Parallel Computing. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1995, pp:101-116 [Conf]
  5. Joydeep Ray, James C. Hoe
    High-level modeling and FPGA prototyping of microprocessors. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:100-107 [Conf]
  6. Peter A. Milder, Mohammad Ahmad, James C. Hoe, Markus Püschel
    Fast and accurate resource estimation of automatically generated custom DFT IP cores. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:211-220 [Conf]
  7. Roland E. Wunderlich, James C. Hoe
    In-system FPGA prototyping of an itanium microarchitecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:255- [Conf]
  8. James C. Hoe, Arvind
    Synthesis of Operation-Centric Hardware Descriptions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:511-518 [Conf]
  9. Markus Püschel, A. C. Zelinski, James C. Hoe
    Custom-optimized multiplierless implementations of DSP algorithms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:175-182 [Conf]
  10. Roland E. Wunderlich, James C. Hoe
    In-System FPGA Prototyping of an Itanium Microarchitecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:288-294 [Conf]
  11. James C. Hoe, Arvind
    Hardware Synthesis from Term Rewriting Systems. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:595-619 [Conf]
  12. Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe
    Statistical sampling of microarchitecture simulation. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  13. Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe
    SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:84-95 [Conf]
  14. Grace Nordin, James C. Hoe
    Synchronous extensions to operation centric hardware description languages. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2004, pp:49-56 [Conf]
  15. Joydeep Ray, James C. Hoe, Babak Falsafi
    Dual use of superscalar datapath for transient-fault detection and recovery. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:214-224 [Conf]
  16. Jared C. Smolens, Jangwoo Kim, James C. Hoe, Babak Falsafi
    Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:257-268 [Conf]
  17. Jared C. Smolens, Brian T. Gold, Babak Falsafi, James C. Hoe
    Reunion: Complexity-Effective Multicore Redundancy. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:223-234 [Conf]
  18. Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe
    TurboSMARTS: accurate microarchitecture simulation sampling in minutes. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2005, pp:408-409 [Conf]
  19. Brian T. Gold, Jangwoo Kim, Jared C. Smolens, Eric S. Chung, Vasileios Liaskovitis, Eriko Nurvitadhi, Babak Falsafi, James C. Hoe, Andreas Nowatzyk
    TRUSS: A Reliable, Scalable Server Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:6, pp:51-59 [Journal]
  20. Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas Nowatzyk
    Fingerprinting: Bounding Soft-Error-Detection Latency and Bandwidth. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:6, pp:22-29 [Journal]
  21. Thomas F. Wenisch, Roland E. Wunderlich, Michael Ferdman, Anastassia Ailamaki, Babak Falsafi, James C. Hoe
    SimFlex: Statistical Sampling of Computer System Simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:4, pp:18-31 [Journal]
  22. Nikolaos Hardavellas, Stephen Somogyi, Thomas F. Wenisch, Roland E. Wunderlich, Shelley Chen, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas Nowatzyk
    SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS Performance Evaluation Review, 2004, v:31, n:4, pp:31-34 [Journal]
  23. James C. Hoe, Arvind
    Operation-centric hardware description and synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1277-1288 [Journal]
  24. Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe
    Statistical sampling of microarchitecture simulation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Model. Comput. Simul., 2006, v:16, n:3, pp:197-224 [Journal]
  25. Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai
    PROToFLEX: FPGA-accelerated Hybrid Functional Simulator. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-6 [Conf]
  26. Forrest Brewer, James C. Hoe
    MEMOCODE 2007 Co-Design Contest. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2007, pp:91-94 [Conf]
  27. John Wawrzynek, David Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic
    RAMP: Research Accelerator for Multiple Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:2, pp:46-57 [Journal]

  28. Dependable VLSI: device, design and architecture: how should they cooperate? [Citation Graph (, )][DBLP]


  29. Formal datapath representation and manipulation for implementing DSP transforms. [Citation Graph (, )][DBLP]


  30. Automatic multithreaded pipeline synthesis from transactional datapath specifications. [Citation Graph (, )][DBLP]


  31. Automatic generation of streaming datapaths for arbitrary fixed permutations. [Citation Graph (, )][DBLP]


  32. Automatic pipelining from transactional datapath specifications. [Citation Graph (, )][DBLP]


  33. Generating FPGA-Accelerated DFT Libraries. [Citation Graph (, )][DBLP]


  34. A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs. [Citation Graph (, )][DBLP]


  35. Real time stereo vision using exponential step cost aggregation on GPU. [Citation Graph (, )][DBLP]


  36. Domain-specific library generation for parallel software and hardware platforms. [Citation Graph (, )][DBLP]


  37. Simulation sampling with live-points. [Citation Graph (, )][DBLP]


  38. MEMOCODE 2008 Co-Design Contest. [Citation Graph (, )][DBLP]


  39. Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding. [Citation Graph (, )][DBLP]


  40. PAI: A Lightweight Mechanism for Single-Node Memory Recovery in DSM Servers. [Citation Graph (, )][DBLP]


  41. Chip-Level Redundancy in Distributed Shared-Memory Multiprocessors. [Citation Graph (, )][DBLP]


Search in 0.190secs, Finished in 0.191secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002