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Sriram Vajapeyam: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Gurindar S. Sohi, Sriram Vajapeyam
    Tradeoffs in Instruction Format Design for Horizontal Architectures. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1989, pp:15-25 [Conf]
  2. Sriram Vajapeyam
    Whither Indian Computer Science R & D? [Citation Graph (0, 0)][DBLP]
    HiPC, 1999, pp:175- [Conf]
  3. Siddhartha V. Tambat, Sriram Vajapeyam
    Non-Strict Cache Coherence: Exploiting Data-Race Tolerance in Emerging Applications. [Citation Graph (0, 0)][DBLP]
    ICPP, 2000, pp:87-94 [Conf]
  4. Gurindar S. Sohi, Sriram Vajapeyam
    Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:27-34 [Conf]
  5. Gurindar S. Sohi, Sriram Vajapeyam
    Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:329-336 [Conf]
  6. Sriram Vajapeyam, P. J. Joseph, Tulika Mitra
    Dynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary Programs. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:16-27 [Conf]
  7. Sriram Vajapeyam, Tulika Mitra
    Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:1-12 [Conf]
  8. Sriram Vajapeyam, Gurindar S. Sohi, Wei-Chung Hsu
    An Empirical Study of the CRAY Y-MP Processor Using the Perfect Club Benchmarks. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:170-179 [Conf]
  9. Sriram Vajapeyam, Wei-Chung Hsu
    On the instruction-level characteristics of scalar code in highly-vectorized scientific applications. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:20-28 [Conf]
  10. Siddhartha V. Tambat, Sriram Vajapeyam
    Page-Level Behavior of Cache Contention. [Citation Graph (0, 0)][DBLP]
    Computer Architecture Letters, 2002, v:1, n:, pp:- [Journal]
  11. James E. Smith, Sriram Vajapeyam
    Trace Processors: Moving to Fourth-Generation Microarchitectures. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:9, pp:68-74 [Journal]
  12. Sriram Vajapeyam, Mateo Valero
    Early 21st Century Processors - Guest Editors' Introduction. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2001, v:34, n:4, pp:47-50 [Journal]
  13. Sriram Vajapeyam, Wei-Chung Hsu
    Toward Effective Scalar Hardware for Highly Vectorizable Applications. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1993, v:19, n:3, pp:147-162 [Journal]

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