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Publications of Author

1. Jared Stark, Marius Evers, Yale N. Patt
   Variable Length Path Branch Prediction. [Citation Graph (0, 0)][DBLP]
   ASPLOS, 1998, pp:170-179 [Conf]
   
2. Marius Evers, Po-Yung Chang, Yale N. Patt
   Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches. [Citation Graph (0, 0)][DBLP]
   ISCA, 1996, pp:3-11 [Conf]
   
3. Marius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt
   An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work. [Citation Graph (0, 0)][DBLP]
   ISCA, 1998, pp:52-61 [Conf]
   
4. Sanjay J. Patel, Marius Evers, Yale N. Patt
   Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. [Citation Graph (0, 0)][DBLP]
   ISCA, 1998, pp:262-271 [Conf]
   
5. Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt
   Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures. [Citation Graph (0, 0)][DBLP]
   MICRO, 1996, pp:191-200 [Conf]
   
6. Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, Jared Stark
   One Billion Transistors, One Uniprocessor, One Chip. [Citation Graph (0, 0)][DBLP]
   IEEE Computer, 1997, v:30, n:9, pp:51-57 [Journal]
   
7. Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt
   Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures. [Citation Graph (0, 0)][DBLP]
   International Journal of Parallel Programming, 1998, v:26, n:4, pp:449-478 [Journal]
   
8. Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari
   Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors. [Citation Graph (0, 0)][DBLP]
   ISPD, 2007, pp:67-74 [Conf]