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Yale N. Patt: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Gregory R. Ganger, Bruce L. Worthington, Robert Y. Hou, Yale N. Patt
    Disk Arrays: High-Performance, High-Reliability Storage Subsystems. [Citation Graph (7, 0)][DBLP]
    IEEE Computer, 1994, v:27, n:3, pp:30-36 [Journal]
  2. Bruce L. Worthington, Gregory R. Ganger, Yale N. Patt
    Scheduling Algorithms for Modern Disk Drives. [Citation Graph (2, 0)][DBLP]
    SIGMETRICS, 1994, pp:241-252 [Conf]
  3. Bruce L. Worthington, Gregory R. Ganger, Yale N. Patt, John Wilkes
    On-Line Extraction of SCSI Disk Drive Parameters. [Citation Graph (2, 0)][DBLP]
    SIGMETRICS, 1995, pp:146-156 [Conf]
  4. Tse-Yu Yeh, Yale N. Patt
    Two-Level Adaptive Training Branch Prediction. [Citation Graph (1, 0)][DBLP]
    MICRO, 1991, pp:51-61 [Conf]
  5. Robert Y. Hou, Yale N. Patt
    Comparing Rebuild Algorithms for Mirrored and RAID5 Disk Arrays. [Citation Graph (1, 10)][DBLP]
    SIGMOD Conference, 1993, pp:317-326 [Conf]
  6. Yale N. Patt
    The I/O Subsystem - A Candidate for Improvement: Guest Editor's Introduction. [Citation Graph (1, 0)][DBLP]
    IEEE Computer, 1994, v:27, n:3, pp:15-16 [Journal]
  7. Jared Stark, Marius Evers, Yale N. Patt
    Variable Length Path Branch Prediction. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1998, pp:170-179 [Conf]
  8. Stephen W. Melvin, Yale N. Patt
    Handling of packet dependencies: a critical issue for highly parallel network processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:202-209 [Conf]
  9. Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt
    Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors. [Citation Graph (0, 0)][DBLP]
    CGO, 2007, pp:367-378 [Conf]
  10. Hyesoon Kim, M. Aater Suleman, Onur Mutlu, Yale N. Patt
    2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set. [Citation Graph (0, 0)][DBLP]
    CGO, 2006, pp:159-172 [Conf]
  11. Alvin M. Despain, Yale N. Patt
    The Aquarius Project. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1984, pp:364-368 [Conf]
  12. Alvin M. Despain, Yale N. Patt
    Aquarius - A High Performance Computing System for Symbolic/Numeric Applications. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1985, pp:376-382 [Conf]
  13. Alvin M. Despain, Yale N. Patt, Tep P. Dobry, Jung-Herng Chang, Wayne Citrin
    High Performance Prolog, The Multiplicative Effect of Several Levels of Implementation. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1986, pp:178-185 [Conf]
  14. Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Chein Chen, Jiajuin Wei
    Experiments with HPS, a Restricted Data Flow Microarchitecture for High Performance Computers. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1986, pp:254-258 [Conf]
  15. Moinuddin K. Qureshi, Onur Mutlu, Yale N. Patt
    Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors. [Citation Graph (0, 0)][DBLP]
    DSN, 2005, pp:434-443 [Conf]
  16. Yale N. Patt
    Higher and Higher Performance Microprocessors: Are The Problems Just Too Hard To Solve? [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1015- [Conf]
  17. Robert Y. Hou, Yale N. Patt
    Using Non-Volatile Storage to Improve the Reliability of RAID5 Disk Arrays. [Citation Graph (0, 0)][DBLP]
    FTCS, 1997, pp:206-215 [Conf]
  18. Yale N. Patt
    The High Performance Microprocessor in the Year 2013: What Will It Look Like? What It Won't Look Like? [Citation Graph (0, 0)][DBLP]
    HiPC, 2003, pp:105- [Conf]
  19. Mary D. Brown, Yale N. Patt
    Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:289-298 [Conf]
  20. Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt
    Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:129-140 [Conf]
  21. Robert Y. Hou, Yale N. Patt
    Trading Disk Capacity for Performance. [Citation Graph (0, 0)][DBLP]
    HPDC, 1993, pp:263-270 [Conf]
  22. Jeff Gee, Stephen W. Melvin, Yale N. Patt
    Advantages of Implementing PROLOG by Microprogramming a Host General Purpose Computer. [Citation Graph (0, 0)][DBLP]
    ICLP, 1987, pp:1-20 [Conf]
  23. Michael Butler, Yale N. Patt
    An Area-Efficient Register Alias Table for Implementing HPS. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1990, pp:611-612 [Conf]
  24. Robert Y. Hou, Yale N. Patt
    Track Piggybacking: An Improved Rebuild Algorithm for RAID5 Disk Arrays. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1995, pp:136-145 [Conf]
  25. Stephen W. Melvin, Yale N. Patt
    Performance benefits of large execution atomic units in dynamically scheduled machines. [Citation Graph (0, 0)][DBLP]
    ICS, 1989, pp:427-432 [Conf]
  26. Paul Racunas, Yale N. Patt
    Partitioned first-level cache design for clustered microarchitectures. [Citation Graph (0, 0)][DBLP]
    ICS, 2003, pp:22-31 [Conf]
  27. John A. Swensen, Yale N. Patt
    Hierarchical registers for scientific computers. [Citation Graph (0, 0)][DBLP]
    ICS, 1988, pp:346-354 [Conf]
  28. Tse-Yu Yeh, Deborah T. Marr, Yale N. Patt
    Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1993, pp:67-76 [Conf]
  29. Yale N. Patt
    A Unifying Theory of Distributed Processing (Or, The Chutzpah One Should Expect When You Invite a Microarchitect into Your Sandbox). [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  30. Michael Butler, Tse-Yu Yeh, Yale N. Patt, Mitch Alsup, Hunter Scales, Michael Shebanow
    Single Instruction Stream Parallelism is Greater Than Two. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:276-286 [Conf]
  31. Po-Yung Chang, Eric Hao, Yale N. Patt
    Target Prediction for Indirect Jumps. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:274-283 [Conf]
  32. Robert S. Chappell, Jared Stark, Sangwook P. Kim, Steven K. Reinhardt, Yale N. Patt
    Simultaneous Subordinate Microthreading (SSMT). [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:186-195 [Conf]
  33. Robert S. Chappell, Francis Tseng, Yale N. Patt, Adi Yoaz
    Difficult-Path Branch Prediction Using Subordinate Microthreads. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:307-317 [Conf]
  34. Tep P. Dobry, Alvin M. Despain, Yale N. Patt
    Performance Studies of a Prolog Machine Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1985, pp:180-190 [Conf]
  35. Marius Evers, Po-Yung Chang, Yale N. Patt
    Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:3-11 [Conf]
  36. Marius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt
    An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:52-61 [Conf]
  37. Wen-mei W. Hwu, Yale N. Patt
    HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:297-306 [Conf]
  38. Wen-mei W. Hwu, Yale N. Patt
    Checkpoint Repair for Out-of-order Execution Machines. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:18-26 [Conf]
  39. Wen-mei W. Hwu, Yale N. Patt
    Retrospective: HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:43-44 [Conf]
  40. Wen-mei W. Hwu, Yale N. Patt
    HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:300-308 [Conf]
  41. Stephen W. Melvin, Yale N. Patt
    Exploiting Fine-Grained Parallelism Through a Combination of Hardware and Software Techniques. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:287-296 [Conf]
  42. Sanjay J. Patel, Marius Evers, Yale N. Patt
    Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:262-271 [Conf]
  43. Yale N. Patt
    Computer Architecture Research and Future Microprocessors: Where Do We Go from Here? [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:2- [Conf]
  44. Onur Mutlu, Hyesoon Kim, Yale N. Patt
    Techniques for Efficient Processing in Runahead Execution Engines. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:370-381 [Conf]
  45. Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt
    A Case for MLP-Aware Cache Replacement. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:167-178 [Conf]
  46. Moinuddin K. Qureshi, David Thompson, Yale N. Patt
    The V-Way Cache: Demand Based Associativity via Global Replacement. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:544-555 [Conf]
  47. Ashok Singhal, Yale N. Patt
    A High Performance Prolog Processor with Multiple Function Units. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:195-202 [Conf]
  48. Eric Sprangle, Robert S. Chappell, Mitch Alsup, Yale N. Patt
    The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:284-291 [Conf]
  49. John A. Swensen, Yale N. Patt
    Fast Temporary Storage for Serial and Parallel Execution. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:35-43 [Conf]
  50. Tse-Yu Yeh, Yale N. Patt
    Alternative Implementations of Two-Level Adaptive Branch Prediction. [Citation Graph (0, 0)][DBLP]
    ISCA, 1992, pp:124-134 [Conf]
  51. Tse-Yu Yeh, Yale N. Patt
    A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:257-266 [Conf]
  52. Tse-Yu Yeh, Yale N. Patt
    Retrospective: Alternative Implementations of Two-Level Adaptive Training Branch Prediction. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:87-88 [Conf]
  53. Tse-Yu Yeh, Yale N. Patt
    Alternative Implementations of Two-Level Adaptive Branch Prediction. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:451-461 [Conf]
  54. Brad Calder, Daniel Citron, Yale N. Patt, J. Smith
    The future of simulation: A field of dreams. [Citation Graph (0, 0)][DBLP]
    ISPASS, 2004, pp:169- [Conf]
  55. Yale N. Patt
    Opening and keynote 1. [Citation Graph (0, 0)][DBLP]
    ISPASS, 2004, pp:1- [Conf]
  56. Mary D. Brown, Jared Stark, Yale N. Patt
    Select-free instruction scheduling logic. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:204-213 [Conf]
  57. Michael Butler, Yale N. Patt
    The Effect of Real Data Cache Behavior on the Performance of a Microarchitecture that Supports Dynamic Scheduling. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:34-41 [Conf]
  58. Michael Butler, Yale N. Patt
    An investigation of the performance of various dynamic scheduling techniques. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:1-9 [Conf]
  59. Michael Butler, Yale N. Patt
    A comparative performance evaluation of various state maintenance mechanisms. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:70-79 [Conf]
  60. David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt
    Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:119-128 [Conf]
  61. Po-Ying Chang, Eric Hao, Yale N. Patt
    Alternative implementations of hybrid branch predictors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:252-257 [Conf]
  62. Po-Yung Chang, Eric Hao, Tse-Yu Yeh, Yale N. Patt
    Branch classification: a new mechanism for improving branch predictor performance. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:22-31 [Conf]
  63. Robert S. Chappell, Francis Tseng, Adi Yoaz, Yale N. Patt
    Microarchitectural support for precomputation microthreads. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:74-84 [Conf]
  64. Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt
    Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:24-33 [Conf]
  65. Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt
    Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:173-181 [Conf]
  66. Wen-mei W. Hwu, Yale N. Patt
    Exploiting horizontal and vertical concurrency via the HPSm microprocessor. [Citation Graph (0, 0)][DBLP]
    MICRO, 1987, pp:154-161 [Conf]
  67. Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt
    Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:191-200 [Conf]
  68. Eric Hao, Po-Yung Chang, Yale N. Patt
    The effect of speculatively updating branch history on branch prediction accuracy, revisited. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:228-232 [Conf]
  69. Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt
    Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:43-54 [Conf]
  70. Onur Mutlu, Hyesoon Kim, Yale N. Patt
    Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:233-244 [Conf]
  71. Yale N. Patt
    Microarchitecture choices (implementation of the VAX). [Citation Graph (0, 0)][DBLP]
    MICRO, 1989, pp:213-216 [Conf]
  72. Stephen W. Melvin, Yale N. Patt
    SPAM: a microcode based tool for tracing operating system events. [Citation Graph (0, 0)][DBLP]
    MICRO, 1987, pp:168-171 [Conf]
  73. Stephen W. Melvin, Michael Shebanow, Yale N. Patt
    Hardware support for large atomic units in dynamically scheduled machines. [Citation Graph (0, 0)][DBLP]
    MICRO, 1988, pp:60-63 [Conf]
  74. Ashok Singhal, Yale N. Patt
    Implementing a Prolog machine with multiple functional units. [Citation Graph (0, 0)][DBLP]
    MICRO, 1988, pp:41-49 [Conf]
  75. Eric Sprangle, Yale N. Patt
    Facilitating superscalar processing via a combined static/dynamic register renaming scheme. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:143-147 [Conf]
  76. Jared Stark, Mary D. Brown, Yale N. Patt
    On pipelining dynamic instruction scheduling logic. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:57-66 [Conf]
  77. Jared Stark, Paul Racunas, Yale N. Patt
    Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:34-43 [Conf]
  78. Tse-Yu Yeh, Yale N. Patt
    A comprehensive instruction fetch mechanism for a processor supporting speculative execution. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:129-139 [Conf]
  79. Tse-Yu Yeh, Yale N. Patt
    Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:164-175 [Conf]
  80. James E. Wilson, Stephen W. Melvin, Michael Shebanow, Wen-mei W. Hwu, Yale N. Patt
    On tuning the microarchitecture of an HPS implementation of the VAX. [Citation Graph (0, 0)][DBLP]
    MICRO, 1987, pp:162-167 [Conf]
  81. Moinuddin K. Qureshi, Yale N. Patt
    Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:423-432 [Conf]
  82. Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt
    Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:53-64 [Conf]
  83. Gregory R. Ganger, Yale N. Patt
    Metadata Update Performance in File Systems. [Citation Graph (0, 0)][DBLP]
    OSDI, 1994, pp:49-60 [Conf]
  84. Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt
    Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2004, pp:2-9 [Conf]
  85. Judith L. Gersting, Peter B. Henderson, Philip Machanick, Yale N. Patt
    Programming early considered harmful. [Citation Graph (0, 0)][DBLP]
    SIGCSE, 2001, pp:402-403 [Conf]
  86. Gregory R. Ganger, Yale N. Patt
    The Process-Flow Model: Examining I/O Performance from the System's Point of View. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1993, pp:86-97 [Conf]
  87. Stephen W. Melvin, Yale N. Patt
    The Use of Microcode Instrumentation for Development, Debugging and Tuning of Operating System Kernels. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1988, pp:207-214 [Conf]
  88. Ashok Singhal, Yale N. Patt
    Unification Parallelism: How Much Can We Exploit? [Citation Graph (0, 0)][DBLP]
    NACLP, 1989, pp:1135-1147 [Conf]
  89. Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt
    Understanding the effects of wrong-path memory references on processor performance. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:56-64 [Conf]
  90. Yale N. Patt
    Variable length tree structures having minimum average search time. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 1969, v:12, n:2, pp:72-76 [Journal]
  91. Yale N. Patt
    Real Machines: Design Choices / Engineering Trade-Offs - Guest Editor's Introduction. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1989, v:22, n:1, pp:8-10 [Journal]
  92. Yale N. Patt
    Experimental Research in Computer Architecture - Guest Editor's Introduction to the Special Issue. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1991, v:24, n:1, pp:14-16 [Journal]
  93. Yale N. Patt
    Identifiying Obstacles in the Path to More. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:12, pp:32- [Journal]
  94. Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, Jared Stark
    One Billion Transistors, One Uniprocessor, One Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:9, pp:51-57 [Journal]
  95. Yale N. Patt
    Microarchitecture, Compilers and Algorithms. [Citation Graph (0, 0)][DBLP]
    ACM Comput. Surv., 1996, v:28, n:4es, pp:33- [Journal]
  96. Yale N. Patt
    First Courses and Fundamentals. [Citation Graph (0, 0)][DBLP]
    ACM Comput. Surv., 1996, v:28, n:4es, pp:99- [Journal]
  97. Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt
    Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1998, v:26, n:4, pp:449-478 [Journal]
  98. Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt
    Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2005, v:33, n:5, pp:529-559 [Journal]
  99. Serafino Amoroso, Gerald Cooper, Yale N. Patt
    Some Clarifications of the Concept of a Garden-of-Eden Configuration. [Citation Graph (0, 0)][DBLP]
    J. Comput. Syst. Sci., 1975, v:10, n:1, pp:77-82 [Journal]
  100. Serafino Amoroso, Yale N. Patt
    Decision Procedures for Surjectivity and Injectivity of Parallel Maps for Tessellation Structures. [Citation Graph (0, 0)][DBLP]
    J. Comput. Syst. Sci., 1972, v:6, n:5, pp:448-464 [Journal]
  101. Howard Jay Siegel, Seth Abraham, William L. Bain, Kenneth E. Batcher, Thomas L. Casavant, Doug DeGroot, Jack B. Dennis, David C. Douglas, Tse-Yun Feng, James R. Goodman, Alan Huang, Harry F. Jordan, J. Robert Jamp, Yale N. Patt, Alan Jay Smith, James E. Smith, Lawrence Snyder, Harold S. Stone, Russ Tuck, Benjamin W. Wah
    Report of the Purdue Workshop on Grand Challenges in Computer Architecture for the Support of High Performance Computing. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1992, v:16, n:3, pp:199-211 [Journal]
  102. Hyesoon Kim, Onur Mutlu, Yale N. Patt, Jared Stark
    Wish Branches: Enabling Adaptive and Aggressive Predicated Execution. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:1, pp:48-58 [Journal]
  103. Onur Mutlu, Hyesoon Kim, Yale N. Patt
    Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:1, pp:10-20 [Journal]
  104. Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt
    Runahead Execution: An Effective Alternative to Large Instruction Windows. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:6, pp:20-25 [Journal]
  105. David B. Aspinwall, Yale N. Patt
    Retrofitting the VAX-11/780 Microarchitecture for IEEE Floating Point Arithmetic - Implementation Issues, Measurements, and Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:8, pp:692-708 [Journal]
  106. Gregory R. Ganger, Yale N. Patt
    Using System-Level Models to Evaluate I/O Subsystem Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:6, pp:667-678 [Journal]
  107. Wen-mei W. Hwu, Yale N. Patt
    Checkpoint Repair for High-Performance Out-of-Order Execution Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:12, pp:1496-1514 [Journal]
  108. Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt
    An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:12, pp:1556-1571 [Journal]
  109. Onur Mutlu, Hyesoon Kim, Yale N. Patt
    Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:12, pp:1491-1508 [Journal]
  110. Sanjay J. Patel, Daniel H. Friendly, Yale N. Patt
    Evaluation of Design Options for the Trace Cache Fetch Mechanism. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:2, pp:193-204 [Journal]
  111. Gregory R. Ganger, Marshall K. McKusick, Craig A. N. Soules, Yale N. Patt
    Soft updates: a solution to the metadata update problem in file systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 2000, v:18, n:2, pp:127-153 [Journal]
  112. Yale N. Patt
    The microprocessor of the year 2014: do Pentium 4, Pentium M, and Power 5 provide any hints? [Citation Graph (0, 0)][DBLP]
    AICCSA, 2005, pp:1- [Conf]
  113. Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer
    Adaptive insertion policies for high performance caching. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:381-391 [Conf]
  114. Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn
    VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:424-435 [Conf]
  115. Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt
    Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:1, pp:94-104 [Journal]

  116. Some results on the asymptotic behavior of functions on subsets of the natural numbers. [Citation Graph (, )][DBLP]


  117. The Challenges of Multicore: Information and Mis-Information. [Citation Graph (, )][DBLP]


  118. Improving the performance of object-oriented languages with dynamic predication of indirect jumps. [Citation Graph (, )][DBLP]


  119. Accelerating critical section execution with asymmetric multi-core architectures. [Citation Graph (, )][DBLP]


  120. Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs. [Citation Graph (, )][DBLP]


  121. Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems. [Citation Graph (, )][DBLP]


  122. The Transformation Hierarchy in the Era of Multi-core. [Citation Graph (, )][DBLP]


  123. Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines. [Citation Graph (, )][DBLP]


  124. Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers. [Citation Graph (, )][DBLP]


  125. Performance-aware speculation control using wrong path usefulness prediction. [Citation Graph (, )][DBLP]


  126. Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems. [Citation Graph (, )][DBLP]


  127. Multi-core demands multi-interfaces. [Citation Graph (, )][DBLP]


  128. Achieving Out-of-Order Performance with Almost In-Order Complexity. [Citation Graph (, )][DBLP]


  129. Flexible reference-counting-based hardware acceleration for garbage collection. [Citation Graph (, )][DBLP]


  130. Data marshaling for multi-core architectures. [Citation Graph (, )][DBLP]


  131. Coordinated control of multiple prefetchers in multi-core systems. [Citation Graph (, )][DBLP]


  132. Improving memory bank-level parallelism in the presence of prefetching. [Citation Graph (, )][DBLP]


  133. Prefetch-Aware DRAM Controllers. [Citation Graph (, )][DBLP]


  134. Multi-core demands multi-interfaces. [Citation Graph (, )][DBLP]


  135. Can They Be Fixed: Some Thoughts After 40 Years in the Business. [Citation Graph (, )][DBLP]


  136. What Else Is Broken? Can We Fix It? [Citation Graph (, )][DBLP]


  137. Dynamic Predication of Indirect Jumps. [Citation Graph (, )][DBLP]


  138. Foreword. [Citation Graph (, )][DBLP]


  139. On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor. [Citation Graph (, )][DBLP]


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