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Amir Roth: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Amir Roth, Andreas Moshovos, Gurindar S. Sohi
    Dependance Based Prefetching for Linked Data Structures. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1998, pp:115-126 [Conf]
  2. Marc L. Corliss, E. Christopher Lewis, Amir Roth
    Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISE. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:303-314 [Conf]
  3. Amir Roth, Gurindar S. Sohi
    Speculative Data-Driven Multithreading. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:37-0 [Conf]
  4. Amir Roth, Andreas Moshovos, Gurindar S. Sohi
    Improving virtual function call target prediction via dependence-based pre-computation. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:356-364 [Conf]
  5. Marc L. Corliss, E. Christopher Lewis, Amir Roth
    DISE: A Programmable Macro Engine for Customizing Applications. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:362-373 [Conf]
  6. Vlad Petric, Tingting Sha, Amir Roth
    RENO - A Rename-Based Instruction Optimizer. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:98-109 [Conf]
  7. Vlad Petric, Amir Roth
    Energy-Effectiveness of Pre-Execution and Energy-Aware P-Thread Selection. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:322-333 [Conf]
  8. Amir Roth
    Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:458-468 [Conf]
  9. Amir Roth, Gurindar S. Sohi
    Effective Jump-Pointer Prefetching for Linked Data Structures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:111-121 [Conf]
  10. Marc L. Corliss, E. Christopher Lewis, Amir Roth
    A DISE implementation of dynamic code decompression. [Citation Graph (0, 0)][DBLP]
    LCTES, 2003, pp:232-243 [Conf]
  11. Anne Bracy, Prashant Prahlad, Amir Roth
    Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:18-29 [Conf]
  12. Vlad Petric, Anne Bracy, Amir Roth
    Three extensions to register integration. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:37-47 [Conf]
  13. Milo M. K. Martin, Amir Roth, Charles N. Fischer
    Exploiting Dead Value Information. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:125-135 [Conf]
  14. Amir Roth, Gurindar S. Sohi
    Register integration: a simple and efficient implementation of squash reuse. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:223-234 [Conf]
  15. Amir Roth, Gurindar S. Sohi
    A quantitative framework for automated pre-execution thread selection. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:430-441 [Conf]
  16. Tingting Sha, Milo M. K. Martin, Amir Roth
    Scalable Store-Load Forwarding via Store Queue Index Prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:159-170 [Conf]
  17. Anne Bracy, Amir Roth
    Serialization-Aware Mini-Graphs: Performance with Fewer Resources. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:171-184 [Conf]
  18. Tingting Sha, Milo M. K. Martin, Amir Roth
    NoSQ: Store-Load Communication without a Store Queue. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:285-296 [Conf]
  19. Gurindar S. Sohi, Amir Roth
    Speculative Multithreaded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2001, v:34, n:4, pp:66-71 [Journal]
  20. Amir Roth, Gurindar S. Sohi
    Squash Reuse via a Simplified Implementation of Register Integration. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2001, v:3, n:, pp:- [Journal]
  21. Marc L. Corliss, E. Christopher Lewis, Amir Roth
    Using DISE to protect return addresses from attack. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:1, pp:65-72 [Journal]
  22. Marc L. Corliss, E. Christopher Lewis, Amir Roth
    The implementation and evaluation of dynamic code decompression using DISE. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:1, pp:38-72 [Journal]
  23. Andrew D. Hilton, Amir Roth
    Ginger: control independence using tag rewriting. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:436-447 [Conf]
  24. Tingting Sha, Milo M. K. Martin, Amir Roth
    NoSQ: Store-Load Communication without a Store Queue. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:1, pp:106-113 [Journal]

  25. CPROB: Checkpoint Processing with Opportunistic Minimal Recovery. [Citation Graph (, )][DBLP]


  26. iCFP: Tolerating all-level cache misses in in-order processors. [Citation Graph (, )][DBLP]


  27. Decoupled store completion/silent deterministic replay: enabling scalable data memory for CPR/CFP processors. [Citation Graph (, )][DBLP]


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