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Daniel J. Sorin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Milo M. K. Martin, Daniel J. Sorin, Anastassia Ailamaki, Alaa R. Alameldeen, Ross M. Dickson, Carl J. Mauer, Kevin E. Moore, Manoj Plakal, Mark D. Hill, David A. Wood
    Timestamp snooping: an approach for extending SMPs. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2000, pp:25-36 [Conf]
  2. Albert Meixner, Daniel J. Sorin
    Unified microprocessor core storage. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2007, pp:23-34 [Conf]
  3. Jonathan R. Carter, Sule Ozev, Daniel J. Sorin
    Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:300-305 [Conf]
  4. Fred A. Bower, Paul G. Shealy, Sule Ozev, Daniel J. Sorin
    Tolerating Hard Faults in Microprocessor Array Structures. [Citation Graph (0, 0)][DBLP]
    DSN, 2004, pp:51-60 [Conf]
  5. Albert Meixner, Daniel J. Sorin
    Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures. [Citation Graph (0, 0)][DBLP]
    DSN, 2006, pp:73-82 [Conf]
  6. Daniel J. Sorin, Mark D. Hill, David A. Wood
    Dynamic Verification of End-to-End Multiprocessor Invariants. [Citation Graph (0, 0)][DBLP]
    DSN, 2003, pp:281-290 [Conf]
  7. Anne Condon, Mark D. Hill, Manoj Plakal, Daniel J. Sorin
    Using Lamport Clocks to Reason about Relaxed Memory Models. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:270-278 [Conf]
  8. Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, David A. Wood
    Bandwidth Adaptive Snooping. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:251-262 [Conf]
  9. Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood
    Using Speculation to Simplify Multiprocessor Design. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  10. E. Ender Bilir, Ross M. Dickson, Ying Hu, Manoj Plakal, Daniel J. Sorin, Mark D. Hill, David A. Wood
    Multicast Snooping: A New Coherence Method Using a Multicast Address Network. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:294-304 [Conf]
  11. Milo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, David A. Wood
    Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:206-217 [Conf]
  12. Albert Meixner, Daniel J. Sorin
    Dynamic Verification of Sequential Consistency. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:482-493 [Conf]
  13. Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood
    SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:123-0 [Conf]
  14. Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mary K. Vernon, David A. Wood
    Analytic Evaluation of Shared-memory Systems with ILP Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:380-391 [Conf]
  15. Jaidev P. Patwardhan, Alvin R. Lebeck, Daniel J. Sorin
    Communication breakdown: analyzing CPU usage in commercial Web workloads. [Citation Graph (0, 0)][DBLP]
    ISPASS, 2004, pp:12-19 [Conf]
  16. Fred A. Bower, Daniel J. Sorin, Sule Ozev
    A Mechanism for Online Diagnosis of Hard Faults in Microprocessors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:197-208 [Conf]
  17. Milo M. K. Martin, Daniel J. Sorin, Harold W. Cain, Mark D. Hill, Mikko H. Lipasti
    Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:328-337 [Conf]
  18. Fred A. Bower, Derek Hower, Mahmut Yilmaz, Daniel J. Sorin, Sule Ozev
    Applying architectural vulnerability Analysis to hard faults in the microprocessor. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS/Performance, 2006, pp:375-376 [Conf]
  19. Derek L. Eager, Daniel J. Sorin, Mary K. Vernon
    AMVA techniques for high service time variability. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2000, pp:217-228 [Conf]
  20. Mark D. Hill, Anne Condon, Manoj Plakal, Daniel J. Sorin
    A System-Level Specification Framework for I/O Architectures. [Citation Graph (0, 0)][DBLP]
    SPAA, 1999, pp:138-147 [Conf]
  21. Tong Li, Alvin R. Lebeck, Daniel J. Sorin
    Quantifying instruction criticality for shared memory multiprocessors. [Citation Graph (0, 0)][DBLP]
    SPAA, 2003, pp:128-137 [Conf]
  22. Manoj Plakal, Daniel J. Sorin, Anne Condon, Mark D. Hill
    Lamport Clocks: Verifying a Directory Cache-Coherence Protocol. [Citation Graph (0, 0)][DBLP]
    SPAA, 1998, pp:67-76 [Conf]
  23. Tong Li, Carla Schlatter Ellis, Alvin R. Lebeck, Daniel J. Sorin
    Pulse: A Dynamic Deadlock Detection Mechanism Using Speculative Execution. [Citation Graph (0, 0)][DBLP]
    USENIX Annual Technical Conference, General Track, 2005, pp:31-44 [Conf]
  24. Alaa R. Alameldeen, Milo M. K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Mark D. Hill, David A. Wood, Daniel J. Sorin
    Simulating a $2M Commercial Server on a $2K PC. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:2, pp:50-57 [Journal]
  25. Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin
    Self-Assembled Architectures and the Temporal Aspects of Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2005, v:38, n:1, pp:56-64 [Journal]
  26. Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin
    NANA: A nano-scale active network architecture. [Citation Graph (0, 0)][DBLP]
    JETC, 2006, v:2, n:1, pp:1-30 [Journal]
  27. Milo M. K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, David A. Wood
    Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:4, pp:92-99 [Journal]
  28. Fred A. Bower, Sule Ozev, Daniel J. Sorin
    Autonomic Microprocessor Execution via Self-Repairing Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Dependable Sec. Comput., 2005, v:2, n:4, pp:297-310 [Journal]
  29. Tong Li, Alvin R. Lebeck, Daniel J. Sorin
    Spin Detection Hardware for Improved Management of Multithreaded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2006, v:17, n:6, pp:508-521 [Journal]
  30. Daniel J. Sorin, Jonathan Lemon, Derek L. Eager, Mary K. Vernon
    Analytic Evaluation of Shared-Memory Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2003, v:14, n:2, pp:166-180 [Journal]
  31. Daniel J. Sorin, Manoj Plakal, Anne Condon, Mark D. Hill, Milo M. K. Martin, David A. Wood
    Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2002, v:13, n:6, pp:556-578 [Journal]
  32. Jonathan R. Carter, Sule Ozev, Daniel J. Sorin
    Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  33. Fred A. Bower, Daniel J. Sorin, Sule Ozev
    Online diagnosis of hard faults in microprocessors. [Citation Graph (0, 0)][DBLP]
    TACO, 2007, v:4, n:2, pp:- [Journal]

  34. Error Detection Using Dynamic Dataflow Verification. [Citation Graph (, )][DBLP]


  35. Verification-Aware Microprocessor Design. [Citation Graph (, )][DBLP]


  36. Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation. [Citation Graph (, )][DBLP]


  37. Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults. [Citation Graph (, )][DBLP]


  38. Specifying and dynamically verifying address translation-aware memory consistency. [Citation Graph (, )][DBLP]


  39. Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching. [Citation Graph (, )][DBLP]


  40. Lazy Error Detection for Microprocessor Functional Units. [Citation Graph (, )][DBLP]


  41. Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms. [Citation Graph (, )][DBLP]


  42. Reduced Precision Checking for a Floating Point Adder. [Citation Graph (, )][DBLP]


  43. Detouring: Translating software to circumvent hard faults in simple cores. [Citation Graph (, )][DBLP]


  44. Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures. [Citation Graph (, )][DBLP]


  45. Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor. [Citation Graph (, )][DBLP]


  46. Dynamic power gating with quality guarantees. [Citation Graph (, )][DBLP]


  47. Argus: Low-Cost, Comprehensive Error Detection in Simple Cores. [Citation Graph (, )][DBLP]


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