The SCEAS System
| |||||||

## Search the dblp DataBase
Paul Chow:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
## Publications of Author- Mazen A. R. Saghir, Paul Chow, Corinna G. Lee
**Exploiting Dual Data-Memory Banks in Digital Signal Processors.**[Citation Graph (0, 0)][DBLP] ASPLOS, 1996, pp:234-243 [Conf] - Tor M. Aamodt, Paul Chow
**Embedded ISA support for enhanced floating-point to fixed-point ANSI-C compilation.**[Citation Graph (0, 0)][DBLP] CASES, 2000, pp:128-137 [Conf] - Ivan Hamer, Paul Chow
**DES Cracking on the Transmogrifier 2a.**[Citation Graph (0, 0)][DBLP] CHES, 1999, pp:13-24 [Conf] - Gennady Feygin, P. Glenn Gulak, Paul Chow
**Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding.**[Citation Graph (0, 0)][DBLP] Data Compression Conference, 1993, pp:118-127 [Conf] - Gennady Feygin, P. Glenn Gulak, Paul Chow
**Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression.**[Citation Graph (0, 0)][DBLP] Data Compression Conference, 1994, pp:254-263 [Conf] - Navid Azizi, Ian Kuon, Aaron Egier, Ahmad Darabiha, Paul Chow
**Reconfigurable Molecular Dynamics Simulator.**[Citation Graph (0, 0)][DBLP] FCCM, 2004, pp:197-206 [Conf] - Lesley Shannon, Paul Chow
**Standardizing the Performance Assessment of Reconfigurable Processor Architectures.**[Citation Graph (0, 0)][DBLP] FCCM, 2003, pp:282-283 [Conf] - Lesley Shannon, Paul Chow
**Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable Controller.**[Citation Graph (0, 0)][DBLP] FCCM, 2005, pp:63-72 [Conf] - Arun Patel, Christopher A. Madill, Manuel Saldaña, Chris Comis, Regis Pomes, Paul Chow
**A Scalable FPGA-based Multiprocessor.**[Citation Graph (0, 0)][DBLP] FCCM, 2006, pp:111-120 [Conf] - Jorge E. Carrillo, Paul Chow
**The effect of reconfigurable units in superscalar processors.**[Citation Graph (0, 0)][DBLP] FPGA, 2001, pp:141-150 [Conf] - P. Glenn Gulak, Paul Chow
**A Field-Programmable Mixed-Analog-Digital Array.**[Citation Graph (0, 0)][DBLP] FPGA, 1995, pp:104-109 [Conf] - Ian Kuon, Navid Azizi, Ahmad Darabiha, Aaron Egier, Paul Chow
**FPGA-based supercomputing: an implementation for molecular dynamics.**[Citation Graph (0, 0)][DBLP] FPGA, 2004, pp:253- [Conf] - David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow
**The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System.**[Citation Graph (0, 0)][DBLP] FPGA, 1997, pp:53-61 [Conf] - Jeffrey A. Jacob, Paul Chow
**Memory Interfacing and Instruction Specification for Reconfigurable Processors.**[Citation Graph (0, 0)][DBLP] FPGA, 1999, pp:145-154 [Conf] - Manuel Saldaña, Lesley Shannon, Paul Chow
**The routability of multiprocessor network topologies in FPGAs.**[Citation Graph (0, 0)][DBLP] FPGA, 2006, pp:232- [Conf] - Lesley Shannon, Paul Chow
**Using reconfigurability to achieve real-time profiling for hardware/software codesign.**[Citation Graph (0, 0)][DBLP] FPGA, 2004, pp:190-199 [Conf] - Paul Chow, Mike Hutton
**Integrating FPGAs in high-performance computing: introduction.**[Citation Graph (0, 0)][DBLP] FPGA, 2007, pp:131- [Conf] - Lesley Shannon, Paul Chow
**Leveraging Reconfigurability in the Design Process.**[Citation Graph (0, 0)][DBLP] FPL, 2005, pp:731-732 [Conf] - Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow
**Designing an FPGA SoC Using a Standardized IP Block Interface.**[Citation Graph (0, 0)][DBLP] FPT, 2005, pp:341-342 [Conf] - Chichyang Chen, Paul Chow
**Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2007, pp:540-545 [Conf] - Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John Paul Shen
**Hardware Support for Prescient Instruction Prefetch.**[Citation Graph (0, 0)][DBLP] HPCA, 2004, pp:84-95 [Conf] - Keith I. Farkas, Norman P. Jouppi, Paul Chow
**How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors?**[Citation Graph (0, 0)][DBLP] HPCA, 1995, pp:78-89 [Conf] - Keith I. Farkas, Norman P. Jouppi, Paul Chow
**Register File Design Considerations in Dynamically Scheduled Processors.**[Citation Graph (0, 0)][DBLP] HPCA, 1996, pp:40-51 [Conf] - Paul Chow, Mark Horowitz
**Architectural Tradeoffs in the Design of MIPS-X.**[Citation Graph (0, 0)][DBLP] ISCA, 1987, pp:300-308 [Conf] - Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
**Memory-System Design Considerations for Dynamically-Scheduled Processors.**[Citation Graph (0, 0)][DBLP] ISCA, 1997, pp:133-143 [Conf] - Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton
**A VLSI Implementation of a Cascade Viterbi Decoder with Traceback.**[Citation Graph (0, 0)][DBLP] ISCAS, 1993, pp:1945-1948 [Conf] - Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
**The Multicluster Architecture: Reducing Cycle Time Through Partitioning.**[Citation Graph (0, 0)][DBLP] MICRO, 1997, pp:149-159 [Conf] - Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang, John Paul Shen
**A framework for modeling and optimization of prescient instruction prefetch.**[Citation Graph (0, 0)][DBLP] SIGMETRICS, 2003, pp:13-24 [Conf] - Manuel Saldaña, Lesley Shannon, Paul Chow
**The routability of multiprocessor network topologies in FPGAs.**[Citation Graph (0, 0)][DBLP] SLIP, 2006, pp:49-56 [Conf] - Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
**The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning.**[Citation Graph (0, 0)][DBLP] International Journal of Parallel Programming, 1999, v:27, n:5, pp:327-356 [Journal] - Gennady Feygin, P. Glenn Gulak, Paul Chow
**Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding.**[Citation Graph (0, 0)][DBLP] Inf. Process. Manage., 1994, v:30, n:6, pp:805-816 [Journal] - L. Louis Zhang, Brent Beacham, Massoud R. Hashemi, Paul Chow, Alberto Leon-Garcia
**A Scheduler ASIC for a Programmable Packet Switch.**[Citation Graph (0, 0)][DBLP] IEEE Micro, 2000, v:20, n:1, pp:42-48 [Journal] - Paul Chow, Zvonko G. Vranesic, Jui Lin Yen
**A Pipelined Distributed Arithmetic PFFT Processor.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1983, v:32, n:12, pp:1128-1136 [Journal] - Manuel Saldaña, Paul Chow
**TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs.**[Citation Graph (0, 0)][DBLP] FPL, 2006, pp:1-6 [Conf] - Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow
**A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification.**[Citation Graph (0, 0)][DBLP] FPL, 2006, pp:1-6 [Conf] - Tor M. Aamodt, Paul Chow
**Optimization of data prefetch helper threads with path-expression based statistical modeling.**[Citation Graph (0, 0)][DBLP] ICS, 2007, pp:210-221 [Conf] - Manuel Saldaña, Lesley Shannon, Jia Shuo Yue, Sikang Bian, John Craig, Paul Chow
**Routability of Network Topologies in FPGAs.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:948-951 [Journal] - Lesley Shannon, Paul Chow
**SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2007, v:15, n:4, pp:377-390 [Journal] - David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow
**The Transmogrifier-2: a 1 million gate rapid-prototyping system.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:188-198 [Journal] **An FPGA Implementation of Reciprocal Sums for SPME.**[Citation Graph (, )][DBLP]**Investigation of Programming Models for Emerging FPGA-Based High Performance Computing Systems.**[Citation Graph (, )][DBLP]**FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy.**[Citation Graph (, )][DBLP]**A high-performance FPGA architecture for restricted boltzmann machines.**[Citation Graph (, )][DBLP]**Acceleration of an analytical approach to collateralized debt obligation pricing.**[Citation Graph (, )][DBLP]**A multi-FPGA architecture for stochastic Restricted Boltzmann Machines.**[Citation Graph (, )][DBLP]**FPGA acceleration of Monte-Carlo based credit derivative pricing.**[Citation Graph (, )][DBLP]**Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture.**[Citation Graph (, )][DBLP]**A Message-Passing Hardware/Software Co-simulation Environment to Aid in Reconfigurable Computing Design Using TMD-MPI.**[Citation Graph (, )][DBLP]
Search in 0.016secs, Finished in 0.018secs | |||||||

| |||||||

| |||||||

System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002 for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002 |