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Joel S. Emer: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Douglas W. Clark, Joel S. Emer
    Performance of the VAX-11/780 Translation Buffer: Simulation and Measurement [Citation Graph (1, 0)][DBLP]
    ACM Trans. Comput. Syst., 1985, v:3, n:1, pp:31-62 [Journal]
  2. Shubhendu S. Mukherjee, Federico Silla, Peter J. Bannon, Joel S. Emer, Steven Lang, David Webb
    A comparative study of arbitration algorithms for the Alpha 21364 pipelined router. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2002, pp:223-234 [Conf]
  3. Eric Borch, Eric Tune, Srilatha Manne, Joel S. Emer
    Loose Loops Sink Chips. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:299-310 [Conf]
  4. Brad Calder, Dirk Grunwald, Joel S. Emer
    Predictive Sequential Associative Cache. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:244-253 [Conf]
  5. Shubhendu S. Mukherjee, Joel S. Emer, Steven K. Reinhardt
    The Soft Error Problem: An Architectural Perspective. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:243-247 [Conf]
  6. Harish Patil, Joel S. Emer
    Combining Static and Dynamic Branch Prediction to Reduce Destructive Aliasing. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:251-0 [Conf]
  7. Joel S. Emer, K. K. Ramakrishnan
    Performance Considerations for Distributed Services: A Case Study: Mass Storage. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1988, pp:289-297 [Conf]
  8. Timothy Sherwood, Brad Calder, Joel S. Emer
    Reducing cache misses using hardware and software page placement. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:155-164 [Conf]
  9. Arijit Biswas, Paul Racunas, Razvan Cheveresan, Joel S. Emer, Shubhendu S. Mukherjee, Ram Rangan
    Computing Architectural Vulnerability Factors for Address-Based Structures. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:532-543 [Conf]
  10. George Z. Chrysos, Joel S. Emer
    Memory Dependence Prediction Using Store Sets. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:142-153 [Conf]
  11. Joel S. Emer, Douglas W. Clark
    A Characterization of Processor Performance in the VAX-11/780. [Citation Graph (0, 0)][DBLP]
    ISCA, 1984, pp:301-310 [Conf]
  12. Joel S. Emer, Douglas W. Clark
    Retrospective: Characterization of Processor Performance in the VAX-11/780. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:37-38 [Conf]
  13. Joel S. Emer, Douglas W. Clark
    A Characterization of Processor Performance in the VAX-11/780. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:274-283 [Conf]
  14. Joel S. Emer, Nicholas C. Gloy
    A Language for Describing Predictors and Its Application to Automatic Synthesis. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:304-314 [Conf]
  15. Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec
    Tarantula: A Vector Extension to the Alpha Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:281-0 [Conf]
  16. Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm
    Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:191-202 [Conf]
  17. Richard Uhlig, David Nagle, Trevor N. Mudge, Stuart Sechrest, Joel S. Emer
    Instruction Fetching: Coping with Code Bloat. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:345-356 [Conf]
  18. Christopher Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt
    Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:264-275 [Conf]
  19. Brad Calder, Dirk Grunwald, Joel S. Emer
    A system level perspective on branch architecture performance. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:199-206 [Conf]
  20. Shubhendu S. Mukherjee, Christopher Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin
    A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:29-42 [Conf]
  21. Craig B. Zilles, Joel S. Emer, Gurindar S. Sohi
    The Use of Multithreading for Exception Handling. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:219-229 [Conf]
  22. Shubhendu S. Mukherjee, Joel S. Emer, Tryggve Fossum, Steven K. Reinhardt
    Cache Scrubbing in Microprocessors: Myth or Necessity? [Citation Graph (0, 0)][DBLP]
    PRDC, 2004, pp:37-42 [Conf]
  23. Joel S. Emer, K. K. Ramakrishnan
    Design analysis of a heterogeneous distributed system. [Citation Graph (0, 0)][DBLP]
    ACM SIGOPS European Workshop, 1986, pp:- [Conf]
  24. Joel S. Emer, Pritpal Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan L. Binkert, Roger Espasa, Toni Juan
    Asim: A Performance Model Framework. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:2, pp:68-76 [Journal]
  25. Shubhendu S. Mukherjee, Sarita V. Adve, Todd M. Austin, Joel S. Emer, Peter S. Magnusson
    Performance Simulation Tools. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:2, pp:38-39 [Journal]
  26. Joel S. Emer
    Incremental Versus Revolutionary Research. [Citation Graph (0, 0)][DBLP]
    ACM Comput. Surv., 1996, v:28, n:4es, pp:27- [Journal]
  27. Shubhendu S. Mukherjee, Chris Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin
    Measuring Architectural Vulnerability Factors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:6, pp:70-75 [Journal]
  28. Christopher Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt
    Reducing the Soft-Error Rate of a High-Performance Microprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:6, pp:30-37 [Journal]
  29. Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen
    Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 1997, v:15, n:3, pp:322-354 [Journal]
  30. K. K. Ramakrishnan, Joel S. Emer
    Performance Analysis of Mass Storage Service Alternatives for Distributed Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1989, v:15, n:2, pp:120-133 [Journal]
  31. Simha Sethumadhavan, Franziska Roesner, Joel S. Emer, Doug Burger, Stephen W. Keckler
    Late-binding: enabling unordered load-store queues. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:347-357 [Conf]
  32. Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer
    Adaptive insertion policies for high performance caching. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:381-391 [Conf]

  33. Adaptive insertion policies for managing shared caches. [Citation Graph (, )][DBLP]


  34. Soft connections: addressing the hardware-design modularity problem. [Citation Graph (, )][DBLP]


  35. A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. [Citation Graph (, )][DBLP]


  36. CAMP: A technique to estimate per-structure power at run-time using a few simple parameters. [Citation Graph (, )][DBLP]


  37. High performance cache replacement using re-reference interval prediction (RRIP). [Citation Graph (, )][DBLP]


  38. Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. [Citation Graph (, )][DBLP]


  39. Accelerating architecture research. [Citation Graph (, )][DBLP]


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