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Jamison D. Collins: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen
Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform. [Citation Graph (0, 0)][DBLP]
ASPLOS, 2004, pp:144-155 [Conf] - Perry H. Wang, Hong Wang, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen
Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. [Citation Graph (0, 0)][DBLP]
HPCA, 2002, pp:187-196 [Conf] - Jamison D. Collins, Dean M. Tullsen
Clustered Multithreaded Architectures - Pursuing both IPC and Cycle Time. [Citation Graph (0, 0)][DBLP]
IPDPS, 2004, pp:- [Conf] - Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher J. Hughes, Yong-Fong Lee, Daniel M. Lavery, John Paul Shen
Speculative precomputation: long-range prefetching of delinquent loads. [Citation Graph (0, 0)][DBLP]
ISCA, 2001, pp:14-25 [Conf] - Richard A. Hankins, Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Ryan Rakvic, Hong Wang, John Paul Shen
Multiple Instruction Stream Processor. [Citation Graph (0, 0)][DBLP]
ISCA, 2006, pp:114-127 [Conf] - Jamison D. Collins, Suleyman Sair, Brad Calder, Dean M. Tullsen
Pointer cache assisted prefetching. [Citation Graph (0, 0)][DBLP]
MICRO, 2002, pp:62-73 [Conf] - Jamison D. Collins, Dean M. Tullsen
Hardware Identification of Cache Conflict Misses. [Citation Graph (0, 0)][DBLP]
MICRO, 1999, pp:126-135 [Conf] - Jamison D. Collins, Dean M. Tullsen, Hong Wang
Control Flow Optimization Via Dynamic Reconvergence Prediction. [Citation Graph (0, 0)][DBLP]
MICRO, 2004, pp:129-140 [Conf] - Jamison D. Collins, Dean M. Tullsen, Hong Wang, John Paul Shen
Dynamic speculative precomputation. [Citation Graph (0, 0)][DBLP]
MICRO, 2001, pp:306-317 [Conf] - Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen
Helper Threads via Virtual Multithreading. [Citation Graph (0, 0)][DBLP]
IEEE Micro, 2004, v:24, n:6, pp:74-82 [Journal] - Jamison D. Collins, Dean M. Tullsen
Runtime identification of cache conflict misses: The adaptive miss buffer. [Citation Graph (0, 0)][DBLP]
ACM Trans. Comput. Syst., 2001, v:19, n:4, pp:413-439 [Journal] - Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Bernard Lint, Asit Mallick, Koichi Yamada, Hong Wang
Sequencer virtualization. [Citation Graph (0, 0)][DBLP]
ICS, 2007, pp:148-157 [Conf] - Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Hong Jiang, Xinmin Tian, Milind Girkar, Nick Y. Yang, Guei-Yuan Lueh, Hong Wang
EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system. [Citation Graph (0, 0)][DBLP]
PLDI, 2007, pp:156-166 [Conf]
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. [Citation Graph (, )][DBLP]
Merge: a programming model for heterogeneous multi-core systems. [Citation Graph (, )][DBLP]
Intel® atomTM processor core made FPGA-synthesizable. [Citation Graph (, )][DBLP]
Intel nehalem processor core made FPGA synthesizable. [Citation Graph (, )][DBLP]
Processor Performance Modeling using Symbolic Simulation. [Citation Graph (, )][DBLP]
CPR: Composable performance regression for scalable multiprocessor models. [Citation Graph (, )][DBLP]
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