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Lu Peng: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Li Yang, Lu Peng
    SecCMP: a secure chip-multiprocessor architecture. [Citation Graph (0, 0)][DBLP]
    ASID, 2006, pp:72-76 [Conf]
  2. Lu Peng, Jih-Kwon Peir, Konrad Lai
    Signature Buffer: Bridging Performance Gap between Registers and Caches. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:164-175 [Conf]
  3. Qianrong Ma, Jih-Kwon Peir, Lu Peng, Konrad Lai
    Symbolic Cache: Fast Memory Access Based on Program Syntax Correlation of Loads and Stores. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:54-61 [Conf]
  4. Xudong Shi, Zhen Yang, Jih-Kwon Peir, Lu Peng, Yen-Kuang Chen, V. Lee, B. Liang
    Coterminous locality and coterminous group data prefetching on chip-multiprocessors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  5. Qiuming Zhu, Lu Peng
    A new approach to conic section approximation of object boundaries. [Citation Graph (0, 0)][DBLP]
    Image Vision Comput., 1999, v:17, n:9, pp:645-658 [Journal]
  6. Lu Peng, Jih-Kwon Peir, Qianrong Ma, Konrad Lai
    Address-free memory access based on program syntax correlation of loads and stores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:314-324 [Journal]

  7. Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics. [Citation Graph (, )][DBLP]


  8. Weak execution ordering - exploiting iterative methods on many-core GPUs. [Citation Graph (, )][DBLP]


  9. Efficient mart-aided modeling for microarchitecture design space exploration and performance prediction. [Citation Graph (, )][DBLP]


  10. Memory Performance and Scalability of Intel's and AMD's Dual-Core Processors: A Case Study. [Citation Graph (, )][DBLP]


  11. Power Efficient IP Lookup with Supernode Caching. [Citation Graph (, )][DBLP]


  12. Expediating IP lookups with reduced power via TBM and SST supernode caching. [Citation Graph (, )][DBLP]


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