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Kartik Mohanram: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alan L. Cox, Kartik Mohanram, Scott Rixner
    Dependable != unaffordable. [Citation Graph (0, 0)][DBLP]
    ASID, 2006, pp:58-62 [Conf]
  2. Abhijit Jas, Kartik Mohanram, Nur A. Touba
    An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:275-0 [Conf]
  3. Quming Zhou, Kartik Mohanram
    Elmore model for energy estimation in RC trees. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:965-970 [Conf]
  4. Quming Zhou, Kartik Mohanram, Athanasios C. Antoulas
    Structure preserving reduction of frequency-dependent interconnect. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:939-942 [Conf]
  5. Quming Zhou, Kai Sun, Kartik Mohanram, Danny C. Sorensen
    Large power grid analysis using domain decomposition. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:27-32 [Conf]
  6. Kartik Mohanram, Nur A. Touba
    Input Ordering in Concurrent Checkers to Reduce Power Consumption. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:87-98 [Conf]
  7. Kartik Mohanram, Nur A. Touba
    Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:433-0 [Conf]
  8. Quming Zhou, Kartik Mohanram
    Cost-effective radiation hardening technique for combinational logic. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:100-106 [Conf]
  9. Mihir R. Choudhury, Quming Zhou, Kartik Mohanram
    Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:204-209 [Conf]
  10. Kartik Mohanram, Egor S. Sogomonyan, Michael Gössel, Nur A. Touba
    Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:35-0 [Conf]
  11. Kartik Mohanram, C. V. Krishna, Nur A. Touba
    A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:577-580 [Conf]
  12. Mosin Mondal, Kartik Mohanram, Yehia Massoud
    Parameter-Variation-Aware Analysis for Noise Robustness. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:655-659 [Conf]
  13. Kartik Mohanram, Nur A. Touba
    Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:893-901 [Conf]
  14. Quming Zhou, Kartik Mohanram
    Analysis of delay caused by bridging faults in RLC interconnects. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1044-1052 [Conf]
  15. Kartik Mohanram, Scott Rixner
    Context-Independent Codes for Off-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
    PACS, 2004, pp:107-119 [Conf]
  16. Kartik Mohanram
    Closed-Form Simulation and Robustness Models for SEU-Tolerant Design. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:327-333 [Conf]
  17. Kartik Mohanram, Nur A. Touba
    Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:121-127 [Conf]
  18. Quming Zhou, Mihir R. Choudhury, Kartik Mohanram
    Design Optimization for Robustness to Single Event Upsets. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:202-207 [Conf]
  19. Quming Zhou, Kartik Mohanram
    Gate sizing to radiation harden combinational logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:155-166 [Journal]
  20. Kartik Mohanram, Nur A. Touba
    Lowering power consumption in concurrent checkers via input ordering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:11, pp:1234-1243 [Journal]
  21. Mihir R. Choudhury, Kartik Mohanram
    Accurate and scalable reliability analysis of logic circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1454-1459 [Conf]
  22. Mihir R. Choudhury, Kyle Ringgenberg, Scott Rixner, Kartik Mohanram
    Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1072-1077 [Conf]

  23. Technology exploration for graphene nanoribbon FETs. [Citation Graph (, )][DBLP]


  24. Timing-driven optimization using lookahead logic circuits. [Citation Graph (, )][DBLP]


  25. Approximate logic circuits for low overhead, non-intrusive concurrent error detection. [Citation Graph (, )][DBLP]


  26. Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis. [Citation Graph (, )][DBLP]


  27. Masking timing errors on speed-paths in logic circuits. [Citation Graph (, )][DBLP]


  28. TIMBER: Time borrowing and error relaying for online timing error resilience. [Citation Graph (, )][DBLP]


  29. Power consumption of logic circuits in ambipolar carbon nanotube technology. [Citation Graph (, )][DBLP]


  30. Analytical model for TDDB-based performance degradation in combinational logic. [Citation Graph (, )][DBLP]


  31. Error Detection and Tolerance for Scaled Electronic Technologies. [Citation Graph (, )][DBLP]


  32. Graphene tunneling FET and its applications in low-power circuit design. [Citation Graph (, )][DBLP]


  33. Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors. [Citation Graph (, )][DBLP]


  34. Dominant critical gate identification for power and yield optimization in logic circuits. [Citation Graph (, )][DBLP]


  35. Parallel domain decomposition for simulation of large-scale power grids. [Citation Graph (, )][DBLP]


  36. Graphene nanoribbon FETs: technology exploration and CAD. [Citation Graph (, )][DBLP]


  37. Power signal processing: a new perspective for power analysis and optimization. [Citation Graph (, )][DBLP]


  38. Modeling stochasticity and robustness in gene regulatory networks. [Citation Graph (, )][DBLP]


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