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## Search the dblp DataBase
Kartik Mohanram:
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## Publications of Author- Alan L. Cox, Kartik Mohanram, Scott Rixner
**Dependable != unaffordable.**[Citation Graph (0, 0)][DBLP] ASID, 2006, pp:58-62 [Conf] - Abhijit Jas, Kartik Mohanram, Nur A. Touba
**An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets.**[Citation Graph (0, 0)][DBLP] Asian Test Symposium, 1999, pp:275-0 [Conf] - Quming Zhou, Kartik Mohanram
**Elmore model for energy estimation in RC trees.**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:965-970 [Conf] - Quming Zhou, Kartik Mohanram, Athanasios C. Antoulas
**Structure preserving reduction of frequency-dependent interconnect.**[Citation Graph (0, 0)][DBLP] DAC, 2005, pp:939-942 [Conf] - Quming Zhou, Kai Sun, Kartik Mohanram, Danny C. Sorensen
**Large power grid analysis using domain decomposition.**[Citation Graph (0, 0)][DBLP] DATE, 2006, pp:27-32 [Conf] - Kartik Mohanram, Nur A. Touba
**Input Ordering in Concurrent Checkers to Reduce Power Consumption.**[Citation Graph (0, 0)][DBLP] DFT, 2002, pp:87-98 [Conf] - Kartik Mohanram, Nur A. Touba
**Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits.**[Citation Graph (0, 0)][DBLP] DFT, 2003, pp:433-0 [Conf] - Quming Zhou, Kartik Mohanram
**Cost-effective radiation hardening technique for combinational logic.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:100-106 [Conf] - Mihir R. Choudhury, Quming Zhou, Kartik Mohanram
**Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques.**[Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:204-209 [Conf] - Kartik Mohanram, Egor S. Sogomonyan, Michael Gössel, Nur A. Touba
**Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits.**[Citation Graph (0, 0)][DBLP] IOLTS, 2003, pp:35-0 [Conf] - Kartik Mohanram, C. V. Krishna, Nur A. Touba
**A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL.**[Citation Graph (0, 0)][DBLP] ISCAS (1), 2002, pp:577-580 [Conf] - Mosin Mondal, Kartik Mohanram, Yehia Massoud
**Parameter-Variation-Aware Analysis for Noise Robustness.**[Citation Graph (0, 0)][DBLP] ISQED, 2007, pp:655-659 [Conf] - Kartik Mohanram, Nur A. Touba
**Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits.**[Citation Graph (0, 0)][DBLP] ITC, 2003, pp:893-901 [Conf] - Quming Zhou, Kartik Mohanram
**Analysis of delay caused by bridging faults in RLC interconnects.**[Citation Graph (0, 0)][DBLP] ITC, 2004, pp:1044-1052 [Conf] - Kartik Mohanram, Scott Rixner
**Context-Independent Codes for Off-Chip Interconnects.**[Citation Graph (0, 0)][DBLP] PACS, 2004, pp:107-119 [Conf] - Kartik Mohanram
**Closed-Form Simulation and Robustness Models for SEU-Tolerant Design.**[Citation Graph (0, 0)][DBLP] VTS, 2005, pp:327-333 [Conf] - Kartik Mohanram, Nur A. Touba
**Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses.**[Citation Graph (0, 0)][DBLP] VTS, 2003, pp:121-127 [Conf] - Quming Zhou, Mihir R. Choudhury, Kartik Mohanram
**Design Optimization for Robustness to Single Event Upsets.**[Citation Graph (0, 0)][DBLP] VTS, 2006, pp:202-207 [Conf] - Quming Zhou, Kartik Mohanram
**Gate sizing to radiation harden combinational logic.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:155-166 [Journal] - Kartik Mohanram, Nur A. Touba
**Lowering power consumption in concurrent checkers via input ordering.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2004, v:12, n:11, pp:1234-1243 [Journal] - Mihir R. Choudhury, Kartik Mohanram
**Accurate and scalable reliability analysis of logic circuits.**[Citation Graph (0, 0)][DBLP] DATE, 2007, pp:1454-1459 [Conf] - Mihir R. Choudhury, Kyle Ringgenberg, Scott Rixner, Kartik Mohanram
**Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory.**[Citation Graph (0, 0)][DBLP] DATE, 2007, pp:1072-1077 [Conf] **Technology exploration for graphene nanoribbon FETs.**[Citation Graph (, )][DBLP]**Timing-driven optimization using lookahead logic circuits.**[Citation Graph (, )][DBLP]**Approximate logic circuits for low overhead, non-intrusive concurrent error detection.**[Citation Graph (, )][DBLP]**Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis.**[Citation Graph (, )][DBLP]**Masking timing errors on speed-paths in logic circuits.**[Citation Graph (, )][DBLP]**TIMBER: Time borrowing and error relaying for online timing error resilience.**[Citation Graph (, )][DBLP]**Power consumption of logic circuits in ambipolar carbon nanotube technology.**[Citation Graph (, )][DBLP]**Analytical model for TDDB-based performance degradation in combinational logic.**[Citation Graph (, )][DBLP]**Error Detection and Tolerance for Scaled Electronic Technologies.**[Citation Graph (, )][DBLP]**Graphene tunneling FET and its applications in low-power circuit design.**[Citation Graph (, )][DBLP]**Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors.**[Citation Graph (, )][DBLP]**Dominant critical gate identification for power and yield optimization in logic circuits.**[Citation Graph (, )][DBLP]**Parallel domain decomposition for simulation of large-scale power grids.**[Citation Graph (, )][DBLP]**Graphene nanoribbon FETs: technology exploration and CAD.**[Citation Graph (, )][DBLP]**Power signal processing: a new perspective for power analysis and optimization.**[Citation Graph (, )][DBLP]**Modeling stochasticity and robustness in gene regulatory networks.**[Citation Graph (, )][DBLP]
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