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Daniel Nussbaum: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Peter Damron, Alexandra Fedorova, Yossi Lev, Victor Luchangco, Mark Moir, Daniel Nussbaum
    Hybrid transactional memory. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:336-346 [Conf]
  2. Victor Luchangco, Daniel Nussbaum, Nir Shavit
    A Hierarchical CLH Queue Lock. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2006, pp:801-810 [Conf]
  3. Anant Agarwal, Jonathan Babb, David Chaiken, Godfrey D'Souza, Kirk L. Johnson, David A. Kranz, John Kubiatowicz, Beng-Hong Lim, Gino Maa, Ken Mackenzie, Daniel Nussbaum, Mike Parkin, Donald Yeung
    Sparcle: A Multithreaded VLSI Processor for Parallel Computing. [Citation Graph (0, 0)][DBLP]
    Parallel Symbolic Computing, 1992, pp:359-361 [Conf]
  4. Daniel Nussbaum, Ingmar Vuong-Adlerberg, Anant Agarwal
    Modeling a Circuit Switched Multiprocessor Interconnect. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1990, pp:267-269 [Conf]
  5. Mark Moir, Daniel Nussbaum, Ori Shalev, Nir Shavit
    Using elimination to implement scalable and lock-free FIFO queues. [Citation Graph (0, 0)][DBLP]
    SPAA, 2005, pp:253-262 [Conf]
  6. Alexandra Fedorova, Margo I. Seltzer, Christopher Small, Daniel Nussbaum
    Performance of Multithreaded Chip Multiprocessors and Implications for Operating System Design. [Citation Graph (0, 0)][DBLP]
    USENIX Annual Technical Conference, General Track, 2005, pp:395-398 [Conf]
  7. Daniel Nussbaum, Anant Agarwal
    Scalability of Parallel Machines. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 1991, v:34, n:3, pp:57-61 [Journal]

  8. Early experience with a commercial hardware transactional memory implementation. [Citation Graph (, )][DBLP]


  9. Chip multithreading systems need a new operating system scheduler. [Citation Graph (, )][DBLP]


  10. The adaptive transactional memory test platform: a tool for experimenting with transactional code for rock (poster). [Citation Graph (, )][DBLP]


  11. Simplifying concurrent algorithms by exploiting hardware transactional memory. [Citation Graph (, )][DBLP]


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