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Benjamin C. Lee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Benjamin C. Lee, David M. Brooks
    Accurate and efficient regression modeling for microarchitectural performance and power prediction. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:185-194 [Conf]
  2. Benjamin C. Lee, Richard W. Vuduc, James Demmel, Katherine A. Yelick
    Performance Models for Evaluation and Automatic Tuning of Symmetric Sparse Matrix-Vector Multiply. [Citation Graph (0, 0)][DBLP]
    ICPP, 2004, pp:169-176 [Conf]
  3. Benjamin C. Lee, David M. Brooks, Bronis R. de Supinski, Martin Schulz, Karan Singh, Sally A. McKee
    Methods of inference and learning for performance modeling of parallel applications. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2007, pp:249-258 [Conf]
  4. Rich Vuduc, James Demmel, Katherine A. Yelick, Shoaib Kamil, Rajesh Nishtala, Benjamin C. Lee
    Performance optimizations and bounds for sparse matrix-vector multiply. [Citation Graph (0, 0)][DBLP]
    SC, 2002, pp:1-35 [Conf]
  5. Benjamin C. Lee
    ACM student research competition finalists - Statistical inference for efficient microarchitectural and application analysis. [Citation Graph (0, 0)][DBLP]
    SC, 2006, pp:191- [Conf]
  6. Benjamin C. Lee
    ACM student research competition reception - Statistical inference for efficient microarchitectural and application analysis. [Citation Graph (0, 0)][DBLP]
    SC, 2006, pp:130- [Conf]
  7. Benjamin C. Lee, David M. Brooks
    Spatial Sampling and Regression Strategies. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:3, pp:74-93 [Journal]

  8. Efficiency trends and limits from comprehensive microarchitectural adaptivity. [Citation Graph (, )][DBLP]


  9. Illustrative Design Space Studies with Microarchitectural Regression Models. [Citation Graph (, )][DBLP]


  10. Roughness of microarchitectural design topologies and its implications for optimization. [Citation Graph (, )][DBLP]


  11. CMP design space exploration subject to physical constraints. [Citation Graph (, )][DBLP]


  12. Architecting phase change memory as a scalable dram alternative. [Citation Graph (, )][DBLP]


  13. Web search using mobile cores: quantifying and mitigating the price of efficiency. [Citation Graph (, )][DBLP]


  14. Understanding sources of inefficiency in general-purpose chips. [Citation Graph (, )][DBLP]


  15. Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis. [Citation Graph (, )][DBLP]


  16. CPR: Composable performance regression for scalable multiprocessor models. [Citation Graph (, )][DBLP]


  17. Better I/O through byte-addressable, persistent memory. [Citation Graph (, )][DBLP]


  18. Phase change memory architecture and the quest for scalability. [Citation Graph (, )][DBLP]


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