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Publications of Author

1. Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
   Introspective 3D chips. [Citation Graph (0, 0)][DBLP]
   ASPLOS, 2006, pp:264-273 [Conf]
   
2. Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar, Laxmi N. Bhuyan
   Power efficient encoding techniques for off-chip data buses. [Citation Graph (0, 0)][DBLP]
   CASES, 2003, pp:267-275 [Conf]
   
3. Shashidhar Mysore, Banit Agrawal, Timothy Sherwood, Nisheeth Shrivastava, Subhash Suri
   Profiling over Adaptive Ranges. [Citation Graph (0, 0)][DBLP]
   CGO, 2006, pp:147-158 [Conf]
   
4. Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee
   A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:991-996 [Conf]
   
5. Dinesh C. Suresh, Jun Yang, Chuanjun Zhang, Banit Agrawal, Walid A. Najjar
   FV-MSB: A Scheme for Reducing Transition Activity on Data Buses. [Citation Graph (0, 0)][DBLP]
   HiPC, 2003, pp:44-54 [Conf]
   
6. Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, Jun Yang
   VALVE: Variable Length Value Encoder for Off-Chip Data Buses.. [Citation Graph (0, 0)][DBLP]
   ICCD, 2005, pp:631-633 [Conf]
   
7. Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar
   A tunable bus encoder for off-chip data buses. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2005, pp:319-322 [Conf]
   
8. Banit Agrawal, Timothy Sherwood
   Virtually Pipelined Network Memory. [Citation Graph (0, 0)][DBLP]
   MICRO, 2006, pp:197-207 [Conf]
   
9. Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
   3D Integration for Introspection. [Citation Graph (0, 0)][DBLP]
   IEEE Micro, 2007, v:27, n:1, pp:77-83 [Journal]
   
10. 
    Understanding and visualizing full systems with data flow tomography. [Citation Graph (, )][DBLP]
    
    
11. 
    Guiding Architectural SRAM Models. [Citation Graph (, )][DBLP]
    
    
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    Modeling TCAM power for next generation network devices. [Citation Graph (, )][DBLP]
    
    
13. 
    A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tags. [Citation Graph (, )][DBLP]
    
    
14. 
    Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation. [Citation Graph (, )][DBLP]
    
    
15. 
    Exploring the Processor and ISA Design for Wireless Sensor Network Applications. [Citation Graph (, )][DBLP]