The SCEAS System
Navigation Menu

Search the dblp DataBase


Cesar Ortega-Sanchez: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Xuan Zhang, Cesar Ortega-Sanchez, Iain Murray
    Hardware-based text-to-braille translator. [Citation Graph (0, 0)][DBLP]
    ASSETS, 2006, pp:229-230 [Conf]
  2. Cesar Ortega-Sanchez, Andrew M. Tyrrell
    Self-Repairing Multicellular Hardware: A Reliability Analysis. [Citation Graph (0, 0)][DBLP]
    ECAL, 1999, pp:442-446 [Conf]
  3. Daryl Bradley, Cesar Ortega-Sanchez, Andrew M. Tyrrell
    Embryonics + Immunotronics: A Bio-Inspired Approach to Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2000, pp:215-224 [Conf]
  4. Cesar Ortega-Sanchez, Andrew M. Tyrrell
    Reliability Analysis in Self-Repairing Embryonic Systems. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 1999, pp:120-128 [Conf]
  5. Cesar Ortega-Sanchez, Andrew M. Tyrrell, Daniel Mange, André Stauffer, Gianluca Tempesti
    Reliability Analysis of a Self-Repairing Embryonic Machine. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1356-1361 [Conf]
  6. Cesar Ortega-Sanchez, Andrew M. Tyrrell
    MUXTREE Revisited: Embryonics as a Reconfiguration Strategy in Fault-Tolerant Processor Arrays. [Citation Graph (0, 0)][DBLP]
    ICES, 1998, pp:206-217 [Conf]
  7. Cesar Ortega-Sanchez, Jose Torres-Jimenez, Jorge Morales-Cruz
    Routing of Embryonic Arrays Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ICES, 2003, pp:249-261 [Conf]
  8. Cesar Ortega-Sanchez, Andrew M. Tyrrell
    A Hardware Implementation of an Embryonic Architecture Using Virtex FPGAs. [Citation Graph (0, 0)][DBLP]
    ICES, 2000, pp:155-164 [Conf]
  9. Cesar Ortega-Sanchez, Daniel Mange, Steve Smith, Andrew M. Tyrrell
    Embryonics: A Bio-Inspired Cellular Architecture with Fault-Tolerant Properties. [Citation Graph (0, 0)][DBLP]
    Genetic Programming and Evolvable Machines, 2000, v:1, n:3, pp:187-215 [Journal]

  10. Reconfigurable PDA for the Visually Impaired Using FPGAs. [Citation Graph (, )][DBLP]

Search in 0.034secs, Finished in 0.035secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002