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Rakesh Patel :
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John C. Grundy , Rakesh Patel Developing Software Components with the UML, Enterprise Java Beans and Aspects. [Citation Graph (0, 0)][DBLP ] Australian Software Engineering Conference, 2001, pp:127-136 [Conf ] Vivek Tiwari , Deo Singh , Suresh Rajgopal , Gaurav Mehta , Rakesh Patel , Franklin Baez Reducing Power in High-Performance Microprocessors. [Citation Graph (0, 0)][DBLP ] DAC, 1998, pp:732-737 [Conf ] Michael Hutton , Vinson Chan , Peter Kazarian , Victor Maruri , Tony Ngai , Jim Park , Rakesh Patel , Bruce Pedersen , Jay Schleicher , Sergey Shumarayev Interconnect enhancements for a high-speed PLD architecture. [Citation Graph (0, 0)][DBLP ] FPGA, 2002, pp:3-10 [Conf ] Lawrence T. Clark , Rakesh Patel , Timothy S. Beatty Managing standby and active mode leakage power in deep sub-micron design. [Citation Graph (0, 0)][DBLP ] ISLPED, 2004, pp:274-279 [Conf ] Fei Li , Lei He , Joseph M. Basile , Rakesh Patel , Hema Ramamurthy High Level Area and Current Estimation. [Citation Graph (0, 0)][DBLP ] PATMOS, 2003, pp:259-268 [Conf ] Subhomoy Chattopadhyay , Rakesh Patel Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2007, pp:5- [Conf ] Search in 0.001secs, Finished in 0.001secs