The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Rakesh Patel: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. John C. Grundy, Rakesh Patel
    Developing Software Components with the UML, Enterprise Java Beans and Aspects. [Citation Graph (0, 0)][DBLP]
    Australian Software Engineering Conference, 2001, pp:127-136 [Conf]
  2. Vivek Tiwari, Deo Singh, Suresh Rajgopal, Gaurav Mehta, Rakesh Patel, Franklin Baez
    Reducing Power in High-Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:732-737 [Conf]
  3. Michael Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh Patel, Bruce Pedersen, Jay Schleicher, Sergey Shumarayev
    Interconnect enhancements for a high-speed PLD architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:3-10 [Conf]
  4. Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty
    Managing standby and active mode leakage power in deep sub-micron design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:274-279 [Conf]
  5. Fei Li, Lei He, Joseph M. Basile, Rakesh Patel, Hema Ramamurthy
    High Level Area and Current Estimation. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:259-268 [Conf]
  6. Subhomoy Chattopadhyay, Rakesh Patel
    Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:5- [Conf]

Search in 0.001secs, Finished in 0.001secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002