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L. E. M. Brackenbury: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mike J. G. Lewis, L. E. M. Brackenbury
    An Instruction Buffer for a Low-Power DSP. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:176-0 [Conf]
  2. Mike J. G. Lewis, L. E. M. Brackenbury
    Exploiting Typical DSP Data Access Patterns and Asynchrony for a Low Power Multiported Register Bank. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:4-14 [Conf]
  3. Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury
    Reconfigurable Latch Controllers for Low Power Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:27-35 [Conf]
  4. Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury
    An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:207-215 [Conf]
  5. P. A. Riocreux, L. E. M. Brackenbury, J. Mike Cumpstey, Stephen B. Furber
    A Low-Power Self-Timed Viterbi Decoder. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:15-24 [Conf]
  6. L. E. M. Brackenbury, W. Shao
    Lowering power in an experimental RISC processor. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:5, pp:360-368 [Journal]

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