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Antonio J. Acosta: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia, Angel Barriga Barrios, Raúl Jiménez, José L. Huertas
    New CMOS VLSI linear self-timed architectures. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1995, pp:14-23 [Conf]
  2. Natividad Martínez Madrid, Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda
    Analog/mixed-signal IP modeling for design reuse. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:766-767 [Conf]
  3. Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda, José L. Huertas
    A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:534-538 [Conf]
  4. Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia
    HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:467-471 [Conf]
  5. Manuel J. Bellido, Manuel Valencia, Antonio J. Acosta, Angel Barriga Barrios, José Luis Huertas, Rafael Domínguez-Castro
    A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2019-2022 [Conf]
  6. Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia
    Gate-level simulation of CMOS circuits using the IDDM model. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:483-486 [Conf]
  7. Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia
    Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:316-326 [Conf]
  8. Raúl Jiménez, Antonio J. Acosta, Eduardo J. Peralías, Adoración Rueda
    An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:295-305 [Conf]
  9. Raúl Jiménez, Pilar Parra, Javier Castro, Manuel Sánchez, Antonio J. Acosta
    Optimization of Master-Slave Flip-Flops for High-Performance Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:439-449 [Conf]
  10. Raúl Jiménez, Pilar Parra, Pedro Sanmartín, Antonio J. Acosta
    A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:209-218 [Conf]
  11. Raúl Jiménez, Pilar Parra, Pedro Sanmartín, Antonio J. Acosta
    A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:491-500 [Conf]
  12. Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia
    Degradation Delay Model Extension to CMOS Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:149-158 [Conf]
  13. Pilar Parra, Antonio J. Acosta, Manuel Valencia
    Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:448-457 [Conf]
  14. T. A. García, Antonio J. Acosta, José L. Huertas, J. M. Mora, J. Ramos
    Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:92-97 [Conf]
  15. Manuel Valencia, Manuel J. Bellido, José L. Huertas, Antonio J. Acosta, Santiago Sánchez-Solano
    Modular Asynchronous Arbiter Insensitive to Metastability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:12, pp:1456-1461 [Journal]
  16. Javier Castro, Pilar Parra, Manuel Valencia, Antonio J. Acosta
    Asymmetric clock driver for improved power and noise performances. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:893-896 [Conf]
  17. Renato Rimolo-Donadio, Antonio J. Acosta, Wolfgang H. Krautschneider
    Asynchronous Staggered Set/Reset Techniques for Low-Noise Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1799-1802 [Conf]
  18. Pilar Parra, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia
    Selective Clock-Gating for Low-Power Synchronous Counters. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:1, pp:11-19 [Journal]

  19. Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures. [Citation Graph (, )][DBLP]


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