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Manuel Valencia: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia, Angel Barriga Barrios, Raúl Jiménez, José L. Huertas
    New CMOS VLSI linear self-timed architectures. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1995, pp:14-23 [Conf]
  2. Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia
    HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:467-471 [Conf]
  3. Manuel J. Bellido, Manuel Valencia, Antonio J. Acosta, Angel Barriga Barrios, José Luis Huertas, Rafael Domínguez-Castro
    A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2019-2022 [Conf]
  4. Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia
    Gate-level simulation of CMOS circuits using the IDDM model. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:483-486 [Conf]
  5. Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia
    Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:316-326 [Conf]
  6. C. Baena, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, C. J. Jiménez, Manuel Valencia
    Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:353-362 [Conf]
  7. Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia
    Degradation Delay Model Extension to CMOS Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:149-158 [Conf]
  8. Pilar Parra, Antonio J. Acosta, Manuel Valencia
    Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:448-457 [Conf]
  9. J. Calvo, J. I. Acha, Manuel Valencia
    Asynchronous Modular Arbiter. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:1, pp:67-70 [Journal]
  10. Manuel Valencia, Manuel J. Bellido, José L. Huertas, Antonio J. Acosta, Santiago Sánchez-Solano
    Modular Asynchronous Arbiter Insensitive to Metastability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:12, pp:1456-1461 [Journal]
  11. Javier Castro, Pilar Parra, Manuel Valencia, Antonio J. Acosta
    Asymmetric clock driver for improved power and noise performances. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:893-896 [Conf]
  12. Pilar Parra, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia
    Selective Clock-Gating for Low-Power Synchronous Counters. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:1, pp:11-19 [Journal]

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