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Marc Renaudin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. F. Aeschlimann, Emmanuel Allier, Laurent Fesquet, Marc Renaudin
    Asynchronous FIR Filters: Towards a New Digital Processing Chain. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:198-206 [Conf]
  2. Emmanuel Allier, Gilles Sicard, Laurent Fesquet, Marc Renaudin
    A New Class of Asynchronous A/D Converters Based on Time Quantization. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:196-205 [Conf]
  3. Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin
    An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2005, pp:54-63 [Conf]
  4. Marc Renaudin, Pascal Vivet, Frédéric Robin
    ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:22-31 [Conf]
  5. Marc Renaudin, Pascal Vivet, Frédéric Robin
    A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:135-144 [Conf]
  6. D. Caucheteux, Edith Beigné, Elisabeth Crochon, Marc Renaudin
    AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2006, pp:86-97 [Conf]
  7. G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin
    Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:384-398 [Conf]
  8. Yannick Monnet, Marc Renaudin, Régis Leveugle
    Asynchronous circuits transient faults sensitivity evaluation. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:863-868 [Conf]
  9. G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain
    DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:424-429 [Conf]
  10. N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin
    FPGA Architecture for Multi-Style Asynchronous Logic. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:32-33 [Conf]
  11. Christian Piguet, Marc Renaudin, Thierry J.-F. Omnés
    Low-power systems on chips (SOCs). [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:488- [Conf]
  12. Marc Renaudin, G. Fraidy Bouesse, Ph. Proust, J. P. Tual, Laurent Sourgen, Fabien Germain
    High Security Smartcards. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:228-233 [Conf]
  13. Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana
    High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1090- [Conf]
  14. Yannick Monnet, Marc Renaudin, Régis Leveugle, Christophe Clavier, Pascal Moitrel
    Case Study of a Fault Attack on Asynchronous DES Crypto-Processors. [Citation Graph (0, 0)][DBLP]
    FDTC, 2006, pp:88-97 [Conf]
  15. Laurent Fesquet, Marc Renaudin
    A Programmable Logic Architecture for Prototyping Clockless Circuits. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:293-298 [Conf]
  16. Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland
    Implementing Asynchronous Circuits on LUT Based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:36-46 [Conf]
  17. Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin
    GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:299-304 [Conf]
  18. Dominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Sirianni
    An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. [Citation Graph (0, 0)][DBLP]
    HICSS, 2003, pp:279- [Conf]
  19. Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin
    Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:313-324 [Conf]
  20. Yannick Monnet, Marc Renaudin, Régis Leveugle
    Asynchronous Circuits Sensitivity to Fault Injection. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:121-128 [Conf]
  21. Yannick Monnet, Marc Renaudin, Régis Leveugle
    Hardening Techniques against Transient Faults for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:129-134 [Conf]
  22. Yannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet
    Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:125-130 [Conf]
  23. Marc Renaudin, Yannick Monnet
    Asynchronous Design: Fault Robustness and Security Characteristics. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:92-95 [Conf]
  24. Gilles Privat, Frédéric Robin, Marc Renaudin, Bachar El Hassan
    A Fine-Grain Asynchronous VLSI Cellular Array Processor Architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1041-1044 [Conf]
  25. Marc Renaudin, Bachar El Hassan
    The Design of Fast Asynchronous Adder Structures and their Implementation Using D.C.V.S. Logic. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:291-294 [Conf]
  26. Emmanuel Allier, J. Goulier, Gilles Sicard, A. Dezzani, E. André, Marc Renaudin
    A 120nm low power asynchronous ADC. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:60-65 [Conf]
  27. Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin
    Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:191-196 [Conf]
  28. Emmanuel Allier, Laurent Fesquet, Marc Renaudin, Gilles Sicard
    Low-Power Asynchronous A/D Conversion. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:81-91 [Conf]
  29. João Leonardo Fragoso, Gilles Sicard, Marc Renaudin
    Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:171-180 [Conf]
  30. Philippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin
    Statistic Implementation of QDI Asynchronous Primitives. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:181-191 [Conf]
  31. Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine
    A Method to Design Compact Dual-rail Asynchronous Primitives. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:571-580 [Conf]
  32. David Rios-Arambula, Aurélien Buhrig, Marc Renaudin
    Power Consumption Reduction Using Dynamic Control of Micro Processor Performance. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:10-18 [Conf]
  33. Eslam Yahya, Marc Renaudin
    QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:583-592 [Conf]
  34. Mohammed Es Salhiene, Laurent Fesquet, Marc Renaudin
    Dynamic Voltage Scheduling for Real Time Asynchronous Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:390-399 [Conf]
  35. Kamel Slimani, Yann Rémond, Gilles Sicard, Marc Renaudin
    TAST Profiler and Low Energy Asynchronous Design Methodology. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:268-277 [Conf]
  36. Laurent Fesquet, Jerome Quartana, Marc Renaudin
    Asynchronous Systems on Programmable Logic. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:105-112 [Conf]
  37. João Leonardo Fragoso, Gilles Sicard, Marc Renaudin
    Automatic Generation of 1-of-M QDI Asynchronous Adders. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:149-154 [Conf]
  38. Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Sirianni
    Validation of asynchronous circuit specifications using IF/CADP. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:86-91 [Conf]
  39. Alain Guyot, Marc Renaudin, Bachar El Hassan, Volker Levering
    Self timed division and square-root extraction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:376-381 [Conf]
  40. Frédéric Robin, Gilles Privat, Marc Renaudin
    Asynchronous Relaxation of Morphological Operators: A Joint Algorithm-Architecture Perspective. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1997, v:11, n:7, pp:1085-1094 [Journal]
  41. Yannick Monnet, Marc Renaudin, Régis Leveugle
    Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:9, pp:1104-1115 [Journal]
  42. Bruno Galilée, Franck Mamalet, Marc Renaudin, Pierre-Yves Coulon
    Parallel Asynchronous Watershed Algorithm-Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:1, pp:44-56 [Journal]
  43. Dhanistha Panyasak, Gilles Sicard, Marc Renaudin
    A current shaping methodology for lowering em disturbances in asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2004, v:35, n:6, pp:531-540 [Journal]
  44. Yannick Monnet, Marc Renaudin, Régis Leveugle
    Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:113-120 [Conf]
  45. Sylvain Miermont, Pascal Vivet, Marc Renaudin
    A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:556-565 [Conf]
  46. Jerome Quartana, Laurent Fesquet, Marc Renaudin
    Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:195-207 [Conf]
  47. Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin
    Security evaluation of dual rail logic against DPA attacks. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:181-186 [Conf]
  48. Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin
    State-holding in Look-Up Tables: application to asynchronous logic. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:12-17 [Conf]
  49. G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard
    Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:11-24 [Conf]
  50. Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin
    Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:55-69 [Conf]
  51. Cedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet
    ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:295-306 [Conf]
  52. G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain
    DPA on quasi delay insensitive asynchronous circuits: formalization and improvement [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  53. N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin
    FPGA Architecture for Multi-Style Asynchronous Logic [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  54. David Rios-Arambula, Aurélien Buhrig, Gilles Sicard, Marc Renaudin
    On the Use of Feedback Systems to Dynamically Control the Supply Voltage of Low-Power Circuits. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:45-55 [Journal]

  55. Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA. [Citation Graph (, )][DBLP]


  56. Comparing transient-fault effects on synchronous and on asynchronous circuits. [Citation Graph (, )][DBLP]


  57. A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications. [Citation Graph (, )][DBLP]


  58. A new analytical approach of the impact of jitter on continuous time delta sigma converters. [Citation Graph (, )][DBLP]


  59. Physical Design of FPGA Interconnect to Prevent Information Leakage. [Citation Graph (, )][DBLP]


  60. Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA. [Citation Graph (, )][DBLP]


  61. The ARESA Project: Facilitating Research, Development and Commercialization of WSNs. [Citation Graph (, )][DBLP]


  62. Timed Asynchronous Circuits Modeling using SystemC. [Citation Graph (, )][DBLP]


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