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Stephen B. Furber: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jim D. Garside, W. J. Bainbridge, Andrew Bardsley, David M. Clark, David A. Edwards, Stephen B. Furber, David W. Lloyd, S. Mohammadi, J. S. Pepper, Steve Temple, J. V. Woods, Jianwei Liu, O. Petli
    AMULET3i - An Asynchronous System-on-Chip. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:162-175 [Conf]
  2. W. J. Bainbridge, Stephen B. Furber
    Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:118-126 [Conf]
  3. W. J. Bainbridge, Stephen B. Furber
    Asynchronous Macrocell Interconnect using MARBLE. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:122-132 [Conf]
  4. W. J. Bainbridge, W. B. Toms, David A. Edwards, Stephen B. Furber
    Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:132-140 [Conf]
  5. Stephen B. Furber, Jim D. Garside, Steve Temple, Jianwei Liu, P. Day, N. C. Paver
    AMULET2e: An Asynchronous Embedded Controller. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1997, pp:290-0 [Conf]
  6. Jim D. Garside, Stephen B. Furber, S.-H. Chung
    AMULET3 Revealed. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:51-59 [Conf]
  7. Z. C. Yu, Stephen B. Furber, Luis A. Plana
    An Investigation into the Security of Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:206-215 [Conf]
  8. O. A. Petlin, Stephen B. Furber
    Built-In Self-Testing of Micropipelines. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1997, pp:22-29 [Conf]
  9. P. A. Riocreux, L. E. M. Brackenbury, J. Mike Cumpstey, Stephen B. Furber
    A Low-Power Self-Timed Viterbi Decoder. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:15-24 [Conf]
  10. Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, J. V. Woods
    AMULET1: A Micropipelined ARM. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1994, pp:476-485 [Conf]
  11. W. J. Bainbridge, Luis A. Plana, Stephen B. Furber
    The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:274-279 [Conf]
  12. Sun-Yen Tan, Stephen B. Furber, Wen-Fang Yen
    The Design of an Asynchronous VHDL Synthesizer. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:44-51 [Conf]
  13. Daranee Hormdee, Jim D. Garside, Stephen B. Furber
    An Asynchronous Victim Cache. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:4-11 [Conf]
  14. Philip Endecott, Stephen B. Furber
    Modelling and Simulation of Asynchronous Systems Using the LARD Hardware Description Language. [Citation Graph (0, 0)][DBLP]
    ESM, 1998, pp:39-43 [Conf]
  15. O. A. Petlin, Stephen B. Furber
    Scan testing of asynchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:224-229 [Conf]
  16. Joy Bose, Stephen B. Furber, Jonathan L. Shapiro
    A Spiking Neural Sparse Distributed Memory Implementation for Learning and Predicting Temporal Sequences. [Citation Graph (0, 0)][DBLP]
    ICANN (1), 2005, pp:115-120 [Conf]
  17. Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, Steve Temple, J. V. Woods
    The Design and Evaluation of an Asynchronous Microprocessor. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:217-220 [Conf]
  18. Stephen B. Furber, David A. Edwards, Jim D. Garside
    AMULET3: A 100 MIPS Asynchronous Embedded Processor. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:329-334 [Conf]
  19. N. C. Paver, P. Day, Stephen B. Furber, Jim D. Garside, J. V. Woods
    Register Locking in an Asynchronous Microprocessor. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:351-355 [Conf]
  20. Yijun Liu, Stephen B. Furber
    The design of a low power asynchronous multiplier. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:301-306 [Conf]
  21. Yijun Liu, Stephen B. Furber
    A Low Power Embedded Dataflow Coprocessor. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:246-247 [Conf]
  22. Stephen B. Furber
    The Return of Asynchronous Logic. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:938- [Conf]
  23. Yijun Liu, Stephen B. Furber
    Minimizing the Power Consumption of an Asynchronous Multiplier. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:289-300 [Conf]
  24. Yijun Liu, Stephen B. Furber
    The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:647-656 [Conf]
  25. Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, J. V. Woods
    A micropipelined ARM. [Citation Graph (0, 0)][DBLP]
    VLSI, 1993, pp:211-220 [Conf]
  26. O. A. Petlin, Stephen B. Furber
    Scan testing of micropipelines. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:296-303 [Conf]
  27. Joy Bose, Stephen B. Furber, Jonathan L. Shapiro
    A System for Transmitting a Coherent Burst of Activity Through a Network of Spiking Neurons. [Citation Graph (0, 0)][DBLP]
    WIRN/NAIS, 2005, pp:44-48 [Conf]
  28. Stephen B. Furber
    Validating the AMULET Microprocessors. [Citation Graph (0, 0)][DBLP]
    Comput. J., 2002, v:45, n:1, pp:19-26 [Journal]
  29. Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple
    Power Management in the Amulet Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:2, pp:42-52 [Journal]
  30. John Bainbridge, Stephen B. Furber
    Chain: A Delay-Insensitive Chip Area Interconnect. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2002, v:22, n:5, pp:16-23 [Journal]
  31. Stephen B. Furber, John Bainbridge, J. Mike Cumpstey, Steve Temple
    Sparse distributed memory using N-of-M codes. [Citation Graph (0, 0)][DBLP]
    Neural Networks, 2004, v:17, n:10, pp:1437-1451 [Journal]
  32. J. V. Woods, P. Day, Stephen B. Furber, Jim D. Garside, N. C. Paver, Steve Temple
    AMULET1: A Asynchronous ARM Microprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:4, pp:385-398 [Journal]
  33. Alexandre Yakovlev, Stephen B. Furber, René Krenz, Alexandre V. Bystrov
    Design and Analysis of a Self-Timed Duplex Communication System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:7, pp:798-814 [Journal]
  34. Daranee Hormdee, Jim D. Garside, Stephen B. Furber
    An asynchronous copy-back cache architecture. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2003, v:27, n:10, pp:485-500 [Journal]
  35. Stephen B. Furber, Steve Temple, A. Brown
    On-chip and inter-chip networks for modeling large-scale neural systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  36. Joy Bose, Stephen B. Furber, Jonathan L. Shapiro
    An associative memory for the on-line recognition and prediction of temporal sequences [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
  37. Stephen B. Furber, P. Day
    Four-phase micropipeline latch control circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:247-253 [Journal]
  38. T. Felicijan, Stephen B. Furber
    An asynchronous ternary logic signaling system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1114-1119 [Journal]

  39. Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million Processors. [Citation Graph (, )][DBLP]


  40. Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system. [Citation Graph (, )][DBLP]


  41. SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network. [Citation Graph (, )][DBLP]


  42. Virtual synaptic interconnect using an asynchronous network-on-chip. [Citation Graph (, )][DBLP]


  43. Efficient modelling of spiking neural networks on a scalable chip multiprocessor. [Citation Graph (, )][DBLP]


  44. SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor. [Citation Graph (, )][DBLP]


  45. Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware. [Citation Graph (, )][DBLP]


  46. A GALS Infrastructure for a Massively Parallel Multiprocessor. [Citation Graph (, )][DBLP]


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