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Publications of Author

1. Jim D. Garside, W. J. Bainbridge, Andrew Bardsley, David M. Clark, David A. Edwards, Stephen B. Furber, David W. Lloyd, S. Mohammadi, J. S. Pepper, Steve Temple, J. V. Woods, Jianwei Liu, O. Petli
   AMULET3i - An Asynchronous System-on-Chip. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2000, pp:162-175 [Conf]
   
2. W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, P. A. Riocreux, Luis A. Plana
   SPA - A Synthesisable Amulet Core for Smartcard pplications. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2002, pp:201-210 [Conf]
   
3. Stephen B. Furber, Jim D. Garside, Steve Temple, Jianwei Liu, P. Day, N. C. Paver
   AMULET2e: An Asynchronous Embedded Controller. [Citation Graph (0, 0)][DBLP]
   ASYNC, 1997, pp:290-0 [Conf]
   
4. Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, Steve Temple, J. V. Woods
   The Design and Evaluation of an Asynchronous Microprocessor. [Citation Graph (0, 0)][DBLP]
   ICCD, 1994, pp:217-220 [Conf]
   
5. Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple
   Power Management in the Amulet Microprocessors. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2001, v:18, n:2, pp:42-52 [Journal]
   
6. Stephen B. Furber, John Bainbridge, J. Mike Cumpstey, Steve Temple
   Sparse distributed memory using N-of-M codes. [Citation Graph (0, 0)][DBLP]
   Neural Networks, 2004, v:17, n:10, pp:1437-1451 [Journal]
   
7. J. V. Woods, P. Day, Stephen B. Furber, Jim D. Garside, N. C. Paver, Steve Temple
   AMULET1: A Asynchronous ARM Microprocessor. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1997, v:46, n:4, pp:385-398 [Journal]
   
8. Luis A. Plana, P. A. Riocreux, W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, Z. C. Yu
   SPA - a secure Amulet core for smartcard applications. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2003, v:27, n:9, pp:431-446 [Journal]
   
9. Stephen B. Furber, Steve Temple, A. Brown
   On-chip and inter-chip networks for modeling large-scale neural systems. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2006, pp:- [Conf]
   
10. 
    A GALS Infrastructure for a Massively Parallel Multiprocessor. [Citation Graph (, )][DBLP]