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Ran Ginosar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Bruce W. Arden, Ran Ginosar
    MP/C: A Multiprocessor/Computer Architecture. [Citation Graph (1, 0)][DBLP]
    ISCA, 1981, pp:3-20 [Conf]
  2. Ran Ginosar
    Fourteen Ways to Fool Your Synchronizer. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:89-97 [Conf]
  3. Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou
    Data Synchronization Issues in GALS SoCs. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:170-180 [Conf]
  4. Rostislav (Reuven) Dobkin, Victoria Vishnyakov, Eyal Friedman, Ran Ginosar
    An Asynchronous Router for Multiple Service Levels Networks on Chip. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2005, pp:44-53 [Conf]
  5. Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun
    Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:80-0 [Conf]
  6. Yaron Semiat, Ran Ginosar
    Timing Measurements of Synchronization Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:68-77 [Conf]
  7. Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny
    Fast Asynchronous Shift Register for Bit-Serial Communication. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2006, pp:117-127 [Conf]
  8. Shai Rotem, Ken S. Stevens, Charles Dike, Marly Roncken, Boris Agapiev, Ran Ginosar, Rakefet Kol, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun
    RAPPID: An Asynchronous Instruction Length Decoder. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:60-70 [Conf]
  9. Ken S. Stevens, Shai Rotem, Ran Ginosar
    Relative Timing. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:208-218 [Conf]
  10. Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny
    High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:3-14 [Conf]
  11. Tsachy Kapschitz, Ran Ginosar
    Formal Verification of Synchronizers. [Citation Graph (0, 0)][DBLP]
    CHARME, 2005, pp:359-362 [Conf]
  12. Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken
    CAD Directions for High Performance Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:116-121 [Conf]
  13. Alex Branover, Rakefet Kol, Ran Ginosar
    Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:870-877 [Conf]
  14. Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
    Efficient link capacity and QoS design for network-on-chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:9-14 [Conf]
  15. Arie Harsat, Ran Ginosar
    CARMEL-2: A Second Generation VLSI Architecture for Flat Concurrent Prolog. [Citation Graph (0, 0)][DBLP]
    FGCS, 1988, pp:962-969 [Conf]
  16. Rakefet Kol, Ran Ginosar
    A Double-Latched Asynchronous Pipeline. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:706-712 [Conf]
  17. Arie Harsat, Ran Ginosar
    An Extended RISC Methodology and its Application to FCP. [Citation Graph (0, 0)][DBLP]
    ICLP, 1990, pp:67-82 [Conf]
  18. Arie Harsat, Ran Ginosar
    CARMEL-4: The Unify-Spawn Machine for FCP. [Citation Graph (0, 0)][DBLP]
    ICLP, 1991, pp:840-854 [Conf]
  19. Ran Ginosar, Dwight D. Hill
    Design and Implementation of Switching Systems for Parallel Processors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1985, pp:674-680 [Conf]
  20. Rakefet Kol, Ran Ginosar
    Kin: A High Performance Asynchronous Processor Architecture. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:433-440 [Conf]
  21. Ilana David, Ran Ginosar, Michael Yoeli
    Self-Timed Architecture of a Reduced Instruction Set Computer. [Citation Graph (0, 0)][DBLP]
    Asynchronous Design Methodologies, 1993, pp:29-43 [Conf]
  22. Bruce W. Arden, Ran Ginosar
    A Single-Relation Module for a Data Base Machine. [Citation Graph (0, 0)][DBLP]
    ISCA, 1981, pp:227-238 [Conf]
  23. Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny
    Low-leakage repeaters for NoC interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:600-603 [Conf]
  24. Ilya Obridko, Ran Ginosar
    Low energy asynchronous architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5238-5241 [Conf]
  25. Uzi Zangi, Ran Ginosar
    A low power video processor. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:136-138 [Conf]
  26. Uri Frank, Ran Ginosar
    A Predictive Synchronizer for Periodic Clock Domains. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:402-412 [Conf]
  27. Uri Frank, Tsachy Kapschitz, Ran Ginosar
    A predictive synchronizer for periodic clock domains. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2006, v:28, n:2, pp:171-186 [Journal]
  28. Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
    Cost considerations in network on chip. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:38, n:1, pp:19-42 [Journal]
  29. Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
    QNoC: QoS architecture and design process for network on chip. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:2-3, pp:105-128 [Journal]
  30. Bruce W. Arden, Ran Ginosar
    MP/C: A Multiprocessor/Computer Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:5, pp:455-473 [Journal]
  31. Ilana David, Ran Ginosar, Michael Yoeli
    An Efficient Implementation of Boolean Functions as Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:1, pp:2-11 [Journal]
  32. Ilana David, Ran Ginosar, Michael Yoeli
    Implementing Sequential Machines as Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:1, pp:12-17 [Journal]
  33. Alan Rotman, Ran Ginosar
    Control unit synthesis from a high-level language. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:162-167 [Journal]
  34. Rostislav (Reuven) Dobkin, Michael Peleg, Ran Ginosar
    Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:427-438 [Journal]
  35. Arkadiy Morgenshtein, Michael Moreinis, Ran Ginosar
    Asynchronous gate-diffusion-input (GDI) circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:8, pp:847-856 [Journal]
  36. Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou
    High Rate Data Synchronization in GALS SoCs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:10, pp:1063-1074 [Journal]
  37. Ilya Obridko, Ran Ginosar
    Minimal Energy Asynchronous Dynamic Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:1043-1047 [Journal]
  38. Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
    Routing table minimization for irregular mesh NoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:942-947 [Conf]
  39. Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny
    The Power of Priority: NoC Based Distributed Cache Coherency. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:117-126 [Conf]
  40. Rostislav (Reuven) Dobkin, Ran Ginosar, Israel Cidon
    QNoC Asynchronous Router with Dynamic Virtual Channel Allocation. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:218- [Conf]
  41. Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny
    Access Regulation to Hot-Modules in Wormhole NoCs. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:137-148 [Conf]
  42. Y. Elboim, Avinoam Kolodny, Ran Ginosar
    A clock-tuning circuit for system-on-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:616-626 [Journal]
  43. Ken S. Stevens, Ran Ginosar, Shai Rotem
    Relative timing [asynchronous design]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:129-140 [Journal]

  44. Performance evaluation of the MP/C. [Citation Graph (, )][DBLP]


  45. Power efficient tree-based crosslinks for skew reduction. [Citation Graph (, )][DBLP]


  46. Timing-driven variation-aware nonuniform clock mesh synthesis. [Citation Graph (, )][DBLP]


  47. The Capacity Allocation Paradox. [Citation Graph (, )][DBLP]


  48. Multiple clock and voltage domains for chip multi processors. [Citation Graph (, )][DBLP]


  49. Fast Universal Synchronizers. [Citation Graph (, )][DBLP]


  50. Parallel vs. serial on-chip communication. [Citation Graph (, )][DBLP]


  51. Timing optimization in logic with interconnect. [Citation Graph (, )][DBLP]


  52. Network-on-Chip Architectures for Neural Networks. [Citation Graph (, )][DBLP]


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