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Hong Wang 0003: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. R. David Weldon, Steven S. Chang, Hong Wang, Gerolf Hoflehner, Perry H. Wang, Daniel M. Lavery, John Paul Shen
    Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2002, pp:57-67 [Conf]
  2. Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen
    Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2004, pp:144-155 [Conf]
  3. Dongkeun Kim, Shih-wei Liao, Perry H. Wang, Juan del Cuvillo, Xinmin Tian, Xiang Zou, Hong Wang, Donald Yeung, Milind Girkar, John Paul Shen
    Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors. [Citation Graph (0, 0)][DBLP]
    CGO, 2004, pp:27-38 [Conf]
  4. Thomas Y. Yeh, Hong Wang
    Redundant Arithmetic Optimizations (Research Note). [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:984-988 [Conf]
  5. Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John Paul Shen
    Hardware Support for Prescient Instruction Prefetch. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:84-95 [Conf]
  6. Perry H. Wang, Hong Wang, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen
    Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:187-196 [Conf]
  7. Perry H. Wang, Hong Wang, Ralph-Michael Kling, Kalpana Ramakrishnan, John Paul Shen
    Register Renaming and Scheduling for Dynamic Execution of Predicated Code. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:15-26 [Conf]
  8. Ed Grochowski, Ronny Ronen, John Paul Shen, Hong Wang
    Best of Both Latency and Throughput. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:236-243 [Conf]
  9. Hong Wang, Qing Yang
    Prime Cube Graph Approach for Processor Allocation in Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:25-32 [Conf]
  10. Qing Yang, Hong Wang
    On Fault-Tolerant Computation of Orthogonal Transforms on Hypercube Computers. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1992, pp:253-256 [Conf]
  11. Satish Narayanasamy, Hong Wang, Perry H. Wang, John Paul Shen, Brad Calder
    A Dependency Chain Clustered Microarchitecture. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  12. Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher J. Hughes, Yong-Fong Lee, Daniel M. Lavery, John Paul Shen
    Speculative precomputation: long-range prefetching of delinquent loads. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:14-25 [Conf]
  13. Richard A. Hankins, Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Ryan Rakvic, Hong Wang, John Paul Shen
    Multiple Instruction Stream Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:114-127 [Conf]
  14. Hong Wang, Tong Sun, Qing Yang
    CAT - Caching Address Tags: A Technique for Reducing Area Cost of On-Chip Caches. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:381-390 [Conf]
  15. Hong Wang, Shiri Manor, Dave LaFollette, Nadav Nesher, Ku-Jei King, Perry H. Wang, Shay Levy, Shai Satt, Gal Carmeli, Arjun Kapur, Ioannis Schoinas, Ed Rubinstein, Rahul Bhatt
    Inferno: a functional simulation infrastructure for modeling microarchitectural data speculations. [Citation Graph (0, 0)][DBLP]
    ISPASS, 2003, pp:11-21 [Conf]
  16. Jamison D. Collins, Dean M. Tullsen, Hong Wang
    Control Flow Optimization Via Dynamic Reconvergence Prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:129-140 [Conf]
  17. Jamison D. Collins, Dean M. Tullsen, Hong Wang, John Paul Shen
    Dynamic speculative precomputation. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:306-317 [Conf]
  18. Shih-wei Liao, Perry H. Wang, Hong Wang, John Paul Shen, Gerolf Hoflehner, Daniel M. Lavery
    Post-Pass Binary Adaptation for Software-Based Speculative Precomputation. [Citation Graph (0, 0)][DBLP]
    PLDI, 2002, pp:117-128 [Conf]
  19. Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang, John Paul Shen
    A framework for modeling and optimization of prescient instruction prefetch. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2003, pp:13-24 [Conf]
  20. Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Bernard Lint, Asit Mallick, Koichi Yamada, Hong Wang
    Sequencer virtualization. [Citation Graph (0, 0)][DBLP]
    ICS, 2007, pp:148-157 [Conf]
  21. Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Hong Jiang, Xinmin Tian, Milind Girkar, Nick Y. Yang, Guei-Yuan Lueh, Hong Wang
    EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system. [Citation Graph (0, 0)][DBLP]
    PLDI, 2007, pp:156-166 [Conf]

  22. Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. [Citation Graph (, )][DBLP]


  23. Merge: a programming model for heterogeneous multi-core systems. [Citation Graph (, )][DBLP]


  24. BLoG: post-silicon bug localization in processors using bug localization graphs. [Citation Graph (, )][DBLP]


  25. Intel® atomTM processor core made FPGA-synthesizable. [Citation Graph (, )][DBLP]


  26. Intel nehalem processor core made FPGA synthesizable. [Citation Graph (, )][DBLP]


  27. Criticality-based optimizations for efficient load processing. [Citation Graph (, )][DBLP]


  28. Processor Performance Modeling using Symbolic Simulation. [Citation Graph (, )][DBLP]


  29. CPR: Composable performance regression for scalable multiprocessor models. [Citation Graph (, )][DBLP]


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