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Mark R. Greenstreet: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mark R. Greenstreet
    Real-Time Merging. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:186-0 [Conf]
  2. Mark R. Greenstreet, Tarik Ono-Tesfaye
    A Fast, asP*, RGD Arbiter. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:173-185 [Conf]
  3. Mark R. Greenstreet, Brian de Alwis
    How to Achieve Worst-Case Performance. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:206-0 [Conf]
  4. Mark R. Greenstreet, Brian D. Winters
    A Negative-Overhead, Self-Timed Pipeline. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:37-46 [Conf]
  5. Mark R. Greenstreet, Anthony Winstanley, Aurelien Garivier
    An Event Spacing Experiment. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:47-0 [Conf]
  6. Ajanta Chakraborty, Mark R. Greenstreet
    Efficient Self-Timed Interfaces for Crossing Clock Domains. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:78-88 [Conf]
  7. Suwen Yang, Brian D. Winters, Mark R. Greenstreet
    Energy Efficient Surfing. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2005, pp:2-11 [Conf]
  8. Tarik Ono-Tesfaye, Christoph Kern, Mark R. Greenstreet
    Verifying a Self-Timed Divider. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:146-158 [Conf]
  9. Peggy B. K. Pang, Mark R. Greenstreet
    Self-Timed Meshes Are Faster Than Synchronous. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1997, pp:30-0 [Conf]
  10. Mark R. Greenstreet, Jihong Ren
    Surfing Interconnect. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2006, pp:98-106 [Conf]
  11. Suwen Yang, Mark R. Greenstreet, Jihong Ren
    A Jitter Attenuating Timing Chain. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:25-38 [Conf]
  12. Mark R. Greenstreet
    Verifying Safety Properties of Differential Equations. [Citation Graph (0, 0)][DBLP]
    CAV, 1996, pp:277-287 [Conf]
  13. Anthony Winstanley, Mark R. Greenstreet
    Temporal Properties of Self-Timed Rings. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:140-154 [Conf]
  14. Jihong Ren, Mark R. Greenstreet
    Synthesizing optimal filters for crosstalk-cancellation for high-speed buses. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:592-597 [Conf]
  15. Jihong Ren, Mark R. Greenstreet
    A unified optimization framework for equalization filter synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:638-643 [Conf]
  16. Mark R. Greenstreet, Ian Mitchell
    Integrating Projections. [Citation Graph (0, 0)][DBLP]
    HSCC, 1998, pp:159-174 [Conf]
  17. Mark R. Greenstreet, Ian Mitchell
    Reachability Analysis Using Polygonal Projections. [Citation Graph (0, 0)][DBLP]
    HSCC, 1999, pp:103-116 [Conf]
  18. Suwen Yang, Mark R. Greenstreet
    Noise margin analysis for dynamic logic circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:406-412 [Conf]
  19. Mark R. Greenstreet
    Implementing a STARI chip. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:38-43 [Conf]
  20. Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger
    Automatic Verification of Refinement. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:225-229 [Conf]
  21. Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton
    Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:267-274 [Conf]
  22. Jihong Ren, Mark R. Greenstreet
    A Signal Integrity Test Bed for PCB Buses. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:132-137 [Conf]
  23. Mark R. Greenstreet
    Using Synchronized Transitions for Simulation and Timing Verification. [Citation Graph (0, 0)][DBLP]
    Designing Correct Circuits, 1992, pp:215-236 [Conf]
  24. Jihong Ren, Mark R. Greenstreet
    Equalizing Filter Design for Crosstalk Cancellation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:272-274 [Conf]
  25. Jihong Ren, Mark R. Greenstreet
    Crosstalk Cancellation for Realistic PCB Buses. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:48-57 [Conf]
  26. Christoph Kern, Tarik Ono-Tesfaye, Mark R. Greenstreet
    A Light-Weight Framework for Hardware Verification. [Citation Graph (0, 0)][DBLP]
    TACAS, 1999, pp:330-344 [Conf]
  27. Jørgen Staunstrup, Mark R. Greenstreet
    From High-Level Descriptions to VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    BIT, 1988, v:28, n:3, pp:620-638 [Journal]
  28. Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger
    Automatic Verification of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:1, pp:24-31 [Journal]
  29. Suwen Yang, Mark R. Greenstreet
    Analysing the Robustness of Surfing Circuits. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:153, n:3, pp:65-77 [Journal]
  30. Christoph Kern, Tarik Ono-Tesfaye, Mark R. Greenstreet
    A light-weight framework for hardware verification. [Citation Graph (0, 0)][DBLP]
    STTT, 2001, v:3, n:3, pp:286-313 [Journal]
  31. Christoph Kern, Mark R. Greenstreet
    Formal verification in hardware design: a survey. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:2, pp:123-193 [Journal]
  32. Brian D. Winters, Mark R. Greenstreet
    Surfing: a robust form of wave pipelining using self-timed circuit techniques. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2003, v:27, n:9, pp:409-419 [Journal]
  33. Suwen Yang, Mark R. Greenstreet
    Simulating Improbable Events. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:154-157 [Conf]
  34. Suwen Yang, Mark R. Greenstreet
    Computing synchronizer failure probabilities. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1361-1366 [Conf]

  35. Faster projection based methods for circuit level verification. [Citation Graph (, )][DBLP]


  36. Verifying VLSI Circuits. [Citation Graph (, )][DBLP]


  37. Circuit Level Verification of a High-Speed Toggle. [Citation Graph (, )][DBLP]


  38. Verifying an Arbiter Circuit. [Citation Graph (, )][DBLP]


  39. Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. [Citation Graph (, )][DBLP]


  40. Verifying start-up conditions for a ring oscillator. [Citation Graph (, )][DBLP]


  41. Computation with Energy-Time Trade-Offs: Models, Algorithms and Lower-Bounds. [Citation Graph (, )][DBLP]


  42. Energy Optimal Scheduling on Multiprocessors with Migration. [Citation Graph (, )][DBLP]


  43. Estimating reliability and throughput of source-synchronous wave-pipelined interconnect. [Citation Graph (, )][DBLP]


  44. A modular synchronizing FIFO for NoCs. [Citation Graph (, )][DBLP]


  45. A Survey and Taxonomy of GALS Design Styles. [Citation Graph (, )][DBLP]


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